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You can almost make a (not very good) AND gate by connecting the NMOS To Vdd and PMOS to Vss. The voltages won't reach the rails and the NMOS needs to be sized to be a lot stronger than the PMOS and you end up with a 'floating' state.
@keith are you saying of using NMOS with gate connected to 1st i/p(say A) & Vdd & a PMOS with gate connected to 2nd i/p(say,B) & Vss. When A,B both low => PMOS on,so o/p is low. When A,B both high => NMOS is on,o/p is high.
When A is high,B is low=> Both are ON,but NMOS width made much higher than PMOS so o/p is high ????? Shouldn't NMOS Ron be made higher than PMOS so as to make o/p low
That is what I am suggesting. It depends on the purpose of the original question. If it is "can you make a useful AND gate with 1 PMOS and 1 NMOS" then the answer is no. If it is an academic question to provoke some lateral thinking then I think the answer is still no, but you can get part way there as I suggested. It won't give rail to rail swing and there is an "undefined state" with both transistors OFF though. If you had a depletion NMOS you may be able to come up with something better.
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