analysis of time/area/power in Synopsys.

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priyanka24

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Hi...

I have implemented my VHDL coding in Design compiler and ICC. now i want to do analysis of one of parameter among time/area/power.

so can anybody knows how to do this analysis and how to start for that?
 

DC commands
report_power -nosplit
report_area -nosplit
report_timing -delay max
report_timing -delay min

Or use Prime time
 
vikadik said:
DC commands
report_power -nosplit
report_area -nosplit
report_timing -delay max
report_timing -delay min

Or use Prime time
Click to expand...

but i want to reduce one of the parameter then how to do that?
 

to reduce area, use optimize placement of standard cells to match the ports, but this might increase the power. I am not sure about what you mean time?

---------- Post added at 01:19 ---------- Previous post was at 01:17 ----------

set_fp_placement_strategy -congestion_effort medium -pin_routing_aware on
create_fp_placement -timing_driven
 



what is the command u written in above reply?

actually i want to reduce one of the parameter among three (time/area/power).
 

THe commands in ICC for placement of standard cells.
 

There are tons of approaches to layout that can reduce area and power. One is making sure you have your standard cells that connect to a certain port close to the port.

priyanka , you need to some experimentation with the commands.
 

vikadik said:
There are tons of approaches to layout that can reduce area and power. One is making sure you have your standard cells that connect to a certain port close to the port.

priyanka , you need to some experimentation with the commands.
Click to expand...

what i have to do if i want to do in Design Compiler?

which is easier to do in DC or ICC?
 

DC just converts your rtl to gatelevel. To reduce the number of cells in your gate level netlist you will have to play with constraints or how the design has been coded. In simple terms, larger number of gates in the gate level netlist, larger the area and power.
ICC on the other hand takes this netlist and lays it out. It adds buffers or inverters to compensate for the parasitics of wire lenght to meet the timing. If you don't have an optimized placement strategy, this means you will have more buffers and inverters leading to power and area increase.

Hope this helps.

---------- Post added at 17:05 ---------- Previous post was at 17:04 ----------

One more question? Are you a professional working for the a big MNC or are you going to one of the coaching classes?
 

yes i got what you said.

but actually i want to know what i need to do to reduce any one (time/area/power) of the parameter?

I am student and having project based on this.
 

The best way is to have a layout strategy to reduce Area. Use ICC to do that. Also you can do design partitioning to optimize on area. THese are all suggestion. You need to decide on them.
 

vikadik said:
The best way is to have a layout strategy to reduce Area. Use ICC to do that. Also you can do design partitioning to optimize on area. THese are all suggestion. You need to decide on them.
Click to expand...

I am toatally new in this so not knowing anything regarding this. so dont know how to start on this?
 

First find the ICC user guide, to help you with commands.

1. Create Milkyway with tech file
2. read verilog
3. read sdc
4. set tlu
5. set_delay_calculation
6. derive_pg_connection
7. initialize_floorplan
8. create_rectangular_rings
9. create floorplan strategy using set_fp_placement_strategy
10. preroute_standard_cells
11. insert_diodes
12. do cts
13. do routing
14. do drc and lvs
 


this are all ICC steps that me did it. whats next?
 

BTW,vikadik ,
the fp_placement commands you mentioned, are pre placement commands?
are they must commands? or i can build the floorplane and use place_opt command?
one more question - the is create_fp_placement and create_placement - what what is the difference between the 2...?
thanks!
 

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