Analysing waveforms, scripts for Cadence, spectre

[kamesh419]

pwl file cadence

Dear all,


I am working on "Prediction of Glitches and Hazards at transistor level". I have to analyse glitches and develop metrics to predict them. The anaylsis will be done at transistor level and i have to implement a mechanism to record the incomplete transitions during simulation. To do this I am using various tools of Cadence.

I am generating the netlist (3 bit Adder for example) using synopsys design analyzer. I then create a schematic using Cadence Virtuoso and supply it with input streams. Later I analyse the outputs. This is what I am suppossed to do.

The problem :

1) How can I convert the inputs which are in binary digital format to analog voltages so that i can give them to my schematic as inputs. I have heard about this "BitGen" program which does this but never tried it. Any other Cadence alternatives you can suggest ?

2) How can I record the incomplete transitions during simulation at transistor level.

3) I have to estimate the Glitches and other parameters (like the No.of Glitches etc..). To do this i have to analyse the wave forms and i cannot do this manually. Can any one suggest any good alternative that i can use in this kind of a scenario. I have heard of "OCEAN" scripting language, SKILL, TCL etc.. can they be useful to analyse the wave forms.

4) Can i automate the whole above processes, instead of doing it manually. Like starting cadence tools (SpectreS simulator), giving inputs, and analysing outputs. If so how can i do that ?

A very lengthy post i believe. Please take some time for this newbie and help me out.

Thanks in advance,

kamesh.

P.S : pardon me if this is not the place to post this.

 

[Vamsi Mocherla]

cadence spectre manual

Firstly,

I guess whatever this program called bitgen is,it works. We usually write scripts to convert digital inputs into pwl sources. It is really easy. I guess bit gen does all that stuff. Then in Cadence you can use a vpwlf source which reads from an input file. So, your input file shall have the information in SPICE/Spectre format.

Secondly,the best thing about analog is all the measurements are real. You can measure all the things like glitch area,Code levels. So, you can do it manually.

Finally, you can automate things using OCEAN/SKILL. But nothing can be manipulated at the transistor level. Only thing you can do is the tool automation

 

[kamesh419]

vpwlf

Thanks a lot Vamsi for the reply. Its really helped me to knock of 2 of my problems. But still i have another 2 to confront with, which are prohibiting me to start my project. They are

1) How can I record the incomplete transitions during simulation at transistor level.

2) I have the Transistor Layout of an 8-bit adder and I would like to simulate that circuit using say 200 pwl sources (Using Analog Design Environment/SpectreS Simulator). I get some glitches when i try to analyze the waveforms. what if i want to know the Number of Glitches that are occurring on the waveforms. Obviously i cannot calculate them manually i believe. So any body has a mechanism to analyze waveforms like these and get the number of Glitches in my case.
Some kind of scripting language (or Calculator tool or something like that) you use to analyze wave forms like these ?

Thanks in Advance,
kamesh.

 

[Vamsi Mocherla]

cadence pwl

Dear Kamesh,

Actually, I really do not know why do you want to count the glitches. There will be a glitch at every transition of code. The major glitch will be at the input code transition of 01111111(seven ones) to 1000000.

Well coming to the incomplete transitions, you can compare it to the ideal response and then measure. That is how we do when we design data converters

 

[kamesh419]

pwl cadence

Dear Vamsi,

There has been some work already done in my dept. on glitches. They have analyzed and metrics for their prediction were developed. These metrics were formulated on the basis of gate level simulation with modelsim. But at that time no transistor level design flow was available to conduct more detailed transistor level analysis. Now we have X-FAB 0.6 u technology with us and i have to analyze glitches and test those metrics which were already developed in here. I also have to take Incomplete transitions in account.

Al this time i have been working with digital stuff. so its a bit problematic for me to understand ur replies directly. could you please elabore ur reply for the Incomplete Transitions thing. and how can we compare the Ideal responce (what is ideal responce) with the responce that we get from the circuit.

Thankyou very much for ur time and patience.

Bye,
kamesh

 

[Vamsi Mocherla]

pwlfile format virtuso

Well, an incomplete or a missed transition would be clearly visible. I mean that when you give a ramp input, you would expect the output to be a constantly increasing digital code. So, if the digital code is not increasing linearly, at that point you can say that there is a missed transition.

In the case of DACs, it is clearly visible for a constantly increasing digital code from 00000000 to 11111111 in digital input.

I hope I am clear on this

 

[kamesh419]

spectre pwl

Thanks vamsi. your inputs helped me to start my proj.
I have got one more prob. I have found that Bitgen Program is not installed in our institute unfortunately. so i would like to use TCL scripts to convert digital inputs to PWL sources. I want to know how i can do this ?

Thanks
kamesh.

 

[Vamsi Mocherla]

spectre pwlfile

Dear Kamesh,

I do not know how to use TCL scripts. But, you can find one on web like this one from MIT

https://www-mtl.mit.edu/research/perrottgroup/tools.html#hspc

 

[kamesh419]

spectre dump pwl file

Thank you once again vamsi.

I need to know how the "input file" should look like for the vpwlf source (I have information like at what time i pass what digital inputs to my 8-bit adder). an example file will be better. Then i can use TCl to generate such a file.

If you can give me the logic behind generating this file then that will be great.

Thanks,
kamesh

 

[Vamsi Mocherla]

spectre pwl file

Dear Kamesh,

You vpwlf source file will look more like this. Actually it is a Piece wise linear source, but written from a file.

For example,

V11 NODE1 NODE2 vpwlf <time1> <value1> <time2> <value2> ......
+ <timeN> <valueN> <timeN+1> <valueN+1>.....

Well, coming to your second question, the logic behind the converter program from vector to pwl is like this:

When there is a 1 in digital , the value in analog is VDD
When there is a 0 in digital, the value is VSS.

When there is a transition from 0---->1 or from 1---->0, the rise and fall times come into being

Finally, there seems to be some vector input format when I referred to the HSPICE manual. Please read that

 

[kamesh419]

cadence pwl erzeugen

Thanks a lot vamsi. your inputs helped me a lot.

I have created the pwl source file from digital inputs according to the MIT scripts that you have suggested. The output looks like this.

v_A0 A0 0 pwl '0*(10n)' '3'
+, '0*(10n)+.3n' '3', '1*(10n)' '3'
+, '1*(10n)+.3n' '0', '2*(10n)' '0'
+, '2*(10n)+.3n' '0', '3*(10n)' '0'
+, '3*(10n)+.3n' '3', '4*(10n)' '3'
+, '4*(10n)+.3n' '0', '5*(10n)' '0'
+, '5*(10n)+.3n' '0', '6*(10n)' '0' ..........

This is for a 0.3 n sec rising and falling transitions and 10n sec time spanning for each binary signal.

Since the MIT source file is for H-spice simulations iam not sure whether the same file can be used for spectre/cadence simulations. Do i need to change any thing else or the same file can be used for my simulations as well ?

Where should i keep the pwl file and how do i point to that file for vpwlf source ?

Do i have to join the vpwlf source to my adder with wires or it not necessary ?

I have a snapshot to assist you in here.

**broken link removed**

Thanks in advance,
kamesh.

 

[Vamsi Mocherla]

vpwlf problem

Dear Kamesh,

In the schematic I am seeing, you have not connected the vpwlf source to the inputs. You should connect it using the wire connection to establish electrical connectivity. And in the form you have got, you should enter the path of your file and the file name where it asks for it.

 

[kamesh419]

vpwlf cadence

Dear vamsi,

I have updated the schematic. Here is the link.

**broken link removed**

I tried to simulate it. It gives me an error saying (This is a part of my output.log file)

Simulating `raw/tb_DW01_add_cla_width8' on MYHOSTMACHINE at 4:45:30 PM, Wed Mar 2, 2005.

Notice from spectre during hierarchy flattening.
timeSweep: `stop' has the unusually large value of 100 s.
Error found by spectre during initial setup.
Waveform file
`/home/coworker/kameswar/glitches/SIMULATION/CADENCE/pwlFile5' is
empty.

spectre completes with 1 error, 0 warnings, and 1 notice.
spectre terminated prematurely due to fatal error.

But my pwlFile5 is not empty. a part of my pwlFile5 is as follows.

v_B1 B<1> 0 pwl '0*(10n)' '3'
+, '0*(10n)+.3n' '3', '1*(10n)' '3'
+, '1*(10n)+.3n' '0', '2*(10n)' '0'
+, '2*(10n)+.3n' '0', '3*(10n)' '0'
+, '3*(10n)+.3n' '3', '4*(10n)' '3'
+, '4*(10n)+.3n' '0', '5*(10n)' '0'
+, '5*(10n)+.3n' '0', '6*(10n)' '0'
+, '6*(10n)+.3n' '0', '7*(10n)' '0'
+, '7*(10n)+.3n' '0', '8*(10n)' '0' ... ...... ... ..

I do not understand where the problem is. every thing that i do depends on this small test circuit which iam developing now. Plz help me.

Thanks in advance,
kamesh.

Added after 2 hours 25 minutes:

Dear vamsi,

What I have included in the PWL file above seems to be the netlist description of PWL waveform. Spectre might be expecting a waveform file with simple time-value pairs like the following.

0 3
10e-9 3
10.3e-9 0
20e-9 0
...

my circuit works with this kind of files. but the problem is by using this method I get the digital wave form and not the analog one i believe and I cannot model the transitions from 1-->0 and from 0-->1, like using raising and falling times.

Can i make use of my netlist description of PWL waveform in any way so that i get the analog description of a wave and not a digital one ? or can i use your method to do this in any different way ?

Thanks in advance,
kamesh.

 

[Vamsi Mocherla]

spectre format

Dear Kamesh,

First things first.....The error you are getting is that the simulation time is too long. Why dont you reduce your simulation time?Then check the results. Try few milliseconds for a start. If you are having rise and fall times in the order of few ns and other signals changing in the same time, the thumb rule is not to run the simulation for more than 10K times the clock in the case of Nyquist converters.

In your pwl file, you should have '+' preceeding every line from the second line onwards. Only then SPICE will think that it is a single line but in continous pattern.

SPECTRE will also follow a similar format. In spectre for it to ensure that it is a continous len, you should have a "\" at the end of the line

 

[kamesh419]

data converters simulation in cadence spectre

Dear Vamsi,

I have reduced the simulation time and i do not get that error now. Thank you once again.

As you have said i have changed the PWL files i.e i have added a \ at the end of each line and there is a + at the begining of each line as shown in below.

The 'pwlFile5'

v_B1 B<1> 0 pwl '0*(10n)' '3'
+, '0*(10n)+.3n' '3', '1*(10n)' '3'\
+, '1*(10n)+.3n' '0', '2*(10n)' '0'\
+, '2*(10n)+.3n' '0', '3*(10n)' '0'\
+, '3*(10n)+.3n' '3', '4*(10n)' '3'\
+, '4*(10n)+.3n' '0', '5*(10n)' '0'\
+, '5*(10n)+.3n' '0', '6*(10n)' '0'\
+, TD '.4n'

Now i get the error

Error found by spectre during initial setup. Waveform file `/home/coworker/kameswar/glitches/SIMULATION/CADENCE/pwlFile5' is empty.
spectre completes with 1 error, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

But my 'pwlFile5' is not empty and it contains the lines that i have shown above.

I was able to simulate the circuit when i change the pwl file to simple time-value pairs like as follows

0 3
10e-9 3
10.3e-9 0
20e-9 0
...

Am i going in the wrong direction or something i dont know.

Thanks and Regards,
kamesh.

 

[Vamsi Mocherla]

cadence scripts

Dear Kamesh,

Likewise i have said, the format I have given is for SPICE. I notice that you are working on spectre. If you can plot the input waveform, then you have a valid file.

 

[kamesh419]

input vector file for spectre

Every problem that i had seems to have been solved now. Thanks a lot for your time and patience vamsi. Now i will be going to my next stage that is writing Verilog-A models to analyze the glitches.

Bye
kamesh