Does anyone know anytool for the analog module characterization?
e.g., suppose I designed a liner driver, I need characterize it to be a verilog model or VHDL model, (even verilog-ams, VHDL-ams), which can be simulatied in the purely digital simulation environment (such as nc-sim) or AMS simulation environment?
Any reference which can help me to understand the procedure how to characterize the analogue module?
Cadence has Aptivia tool. It actualy works halfdecent - as any tool.
What I have experiencied is that good analog model takes as much time to simulate as transistor level. But it is worth to try.