Analog VLSI circuits doubts

[Valiant vince]

1.In Eldo software, where are we supposed to find the process parameters up,un,Cox,lambda?
2.Are the above values for 0.13um applicable to 0.5 um technology or higher?
3.In a CMOS circuit, should 'L' of all MOSFETS be the same?if so why?if no why not?
4.how much error is allowed between simulations done in eldo and throretical calculations?
5.should a MOS in triode region always be modelled by a linear resistor? if no, why not?
6.when should we exactly neglect Vds^2/2 in triode equation for drain current?
7.In a simple common source amplifier with current source load, why is the dc voltage at output not uniquely determined?what is common mode feedback?
8.What exactly is 0.13um technology?L=0.13um only or L>=0.13um?please justify.

 

[naveensai12]

2)No
3)L should be same for all the Tx .We should try using the min L .This is because the area of the Chip reduces and less chip are is less cost to consumers .The longer L are used only in ckts where noise should be less .but preferably the Lmin should be used ..
4)There can be error depending on the approximations you used for calculating the values .It might vary from 10-25pc .
5)modeled in the sense ? are you trying to use a mosfet as a resistor ??

 

[Valiant vince]

thanks for replying
can u answer the rest

5) i meant that when a mosfet in a given big cmos circuit is in deep triode region, is it correct to represent it as a linear resistor Ron(whose value of course depends on VGS)?And this VGS is dc right?or ac?

One more doubt, i find it difficult to differentiate between dc and ac
1. can mosfet be used for dc amplification?or only ac?
2.how to actually view capacitors in analog circuits from the practical point of view?
3.what is meant by 'very large capacitor'?does it mean C=infinity or that physical size of capacitor is more

 

[naveensai12]

5)VGS is DC bias given and this bias determines the region in which the ckt. operates.It will have current which might be be similar to exponential current in a diode and it behaves like a resistor in that region .
1)mosfet amlifies only AC not DC
2)When there is a high freq component it will act as a short and for low freq it will be open .
3)physical size of the cap is more ....

 

[Valiant vince]

Can u pls help with the biasing of MOSFETs in circuit of fig 3 on this link:
https://www.google.co.in/url?sa=t&r...rLqQg2CfxZNDMDLDA&sig2=e6lpgDucvnRiKJrbvVN6Mg

1.Also pls explain the basic idea of enhancing the slew rate.
2.When is the dynamic situation exactly reached i.e. charging/discharging of the load cap CL through drive transistors Mp and Mn?
3.Which exactly are the current mirrors in the circuit?

 

[naveensai12]

the biasing for the circuit can be found in CMOS book by Baker ....
1)Slew rate enhancing is done to charge up the ckt o/p faster .....in SR mode the current from the TX charged the o/p and after a specific voltage is reached the normal operation of TX in saturation mode kicks in .......So if the load is more,SR applies for some time before the normal Ckt operation kicks in....
3)Ma1 and md1 current mirrors .....