Analog pulse modulation-Working circuit

Status
Not open for further replies.
G

gary36

Full Member level 5
Joined
Mar 31, 2018
Messages
241
Helped
0
Reputation
0
Reaction score
0
Trophy points
16
Visit site
Activity points
2,068
I have searched a lot but unable to find working circuit which illustrates flat top, single polarity pulse amplitude modulation. Help required.
 

Sort by date Sort by votes
It is only for academic experiments so specifications does not matter. But I need working circuit with values of passives
 

Upvote 0 Downvote
Flat top PAM. Analyze the trace below. What do you see?

1. Sine wave sample & hold at least 6 times per cycle. It could be more or less but the result may change.
2. A 50 % duty factor of 0V and held sample


So you need a sine gen, a sampler square wave at some variable speed say 6x , a sample & hold and a SPDT analog (MUX) switch and then coordinate the logical tasks of each component into a schematic.

Now go do your homework.

I did not bother to find a better picture than above. Forgive me but the "flat top" sample of the sine wave should "hold" at a pre-defined instant relative to the clock, such as leading edge and not wander to the trailing edge.

ref https://www.elprocus.com/pulse-amplitude-modulation/
 
Last edited:

Upvote 0 Downvote
Many of the links provided by google does not have model/circuit which actually works. I am just looking for that one. I understand the theory.
 

Upvote 0 Downvote
A stiff-enough buffer amp and a switch, after whatever sets the level.

"Stiff enough" is either by open-loop-sizing, or by an outer loop that
trues up the buffer "quick enough" after the edge soaks up load
dV/dt current and sags it.
 

Upvote 0 Downvote
Here's one way using CMOS unipolar , I just tried.

This is an alternate Track & Hold method onto two caps at 1/2 the PAM rate then stores the values with a small RC delay of the 2nd SPDT CMOS switch then finally multiplexed with ground on the 3rd switch. A divide by 2 FF creates the sample clock while the input clock alternates between 0V and the tophat S&H voltage. There are simpler ways low RdsOn and narrow Sample pulse. Never use ceramic for your hold capacitor to avoid voltage sensitive capacitance that causes hysteresis.
Metal film caps are a good choice.




FWIW http://cc.ee.ntu.edu.tw/~wujsh/10101PC/Chapter3_101.11.05.pdf
https://tinyurl.com/ykccpjw3 Falstad Sim
 

Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…