Hi,
I'd like to give you my idea about your first quetion,
if a route carried voltage signal, then the source would be a voltage source. so the route is resistivly sensitive and you'd better be careful the parasitic R when layout.
similarly, when a route carried current, the source would be a current source. the parasitic C may badly slow down the speed.
I would like to answer #4.
This is to have a better current/voltage density and distribution over the metal area connected/covered by the vias.
And, in a via array, let say if 1 via is not working or is not connected, at least you still have the remaining vias to connect the two metal layers. ^^,
#5 - If the Antenna violation can't be solved with switching routing Layers close to gate, tie down diodes are needed. These are reversed biased during circuit operation. During CMP the diodes temperature rises and discharges the gate resistively. The rules for Antenna Violation should be checked in Design Manual
2) If any terminal of device is connected to pad,it may have connection with outer environment.So use ESD devices in such cases.
3)Double guard ring concept is used to avoid latch-up and also it blocks charge injection from substrate.
7)Off-grid errors arise during DRC.The only remedy is delete all off-grid layout and draw new one with grid specified in PDK.
Hope this helps
Best regards
Jarilak.r
"Anyone who has never made a mistake has never tried anything new." - Albert Einstein