analog layout flow and doubts

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p.sivakumar

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Hi to All
I know digital standard cell layouts........
I am new to analog layouts ,so
Can any one explain flow of analog layout from schematic ?What are the constraints we should take to draw analog layouts ?
What is Salicide resister ?what is the difference between salicide and unsalicide resistor ?


Thanks
Siva
 

well for analog layout these constarints u should follow
1- matching level of the transistors,and R,nC.
2-EMIR drops.
3-width of power tracks use highest leve of metal for poewr track .
4-paracitics in the critical brancs(signal carrying lines).
5-avoid the overlaping of the HF lines and biasing .
6- in analog layout the placements is the most important.
7- try to make ur layout symmetrical.
8-use shielding properly in overlaping of the lines where required
9-avoid poly connecton
10- use 1-3-5.. metals horizontal and 2-4-6 metals in vertical direction :arrow:
 
salicide is self alligned silicidation ,
silicidation is adding a refractory metal for poly "polycide" or for contact , resistor .
in all cases it decrease there resistance , where refractory metals "i.e. tangestun W" has lower resistivity than poly or diffusion but ofcourse higher than metals like Cu , Al.
silicides are added to contact cuts before metal to prevent pitting "diffusion of Al,Cu into Si which may cause shorting MOS , this happen due to solubility of Al in Si"

self alligned means that we are doing the silicidation for poly and contacts and resistors in one step.
 

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