Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

[yyy963741tw]

I simulated the example of veriloga tutorial workshop
but with error message that :
Error detected by hpeesofsim during netlist flattening.
`psfetv1' is an instance of an undefined model `psfetv'.
How can i solve it?

 

[pancho_hideboo]

ADS is not an Analog Design System.
It is an Advanced Design System.

Show me netlist.

Simply you don’t include model definition which is described by Verilog-A or ADSsim language.

 

[yyy963741tw]

I am sorry to mistype the word.
how could i inculde th e model
this tutorial example workspace should not already fininshed?

 

[pancho_hideboo]

how could i inculde th e model

Place model definition component in schematic.

this tutorial example workspace should not already fininshed?

I can not understand what you want to mean at all.
Write sentences with correct grammer.

 

[yyy963741tw]

so i should copy the veriloga code into netlist?


I mean this work provided by program tutorial . It Should be able to simulate normally . But it can't

 

[volker@muehlhaus]

Check the schematic in your tutorial. It seems that you missed to add some model/library include block which tells ADS about the model details.