[SOLVED] Analog ADC filtering

[HighTechPower]

Hi. Recently I had to filter some data before giving it to microcontroller ADC. Plz attached here find some techniques that came to my mind. Actually I was using switch mode power supply to power the circuit and was creating erroneous results without filtering as in top figure. Which one is correct, you prefer, why and recommended values?

 

[barry]

The first one is not a filter, it’s a voltage divider. The second two have the exact same filtering, assuming same value components. That series resistor might have some effect, depending on what your ADC input looks like.

there’s no way anyone can “recommend values”, we don’t know anything about your circuit, your application or your requirements.

another thing to think about is averaging in software to reduce noise.

 

[KlausST]

Hi,

I agree with Barry.
The first one is no filter.
The second ine is most often used
The third has a series resistor. Don't know why. I see no reason for it, without detailed informations.

For a correct design you need to know:
* the highest frequency you are interested in processing... and how much it's value may deviate from iseal
( = Upper pass band frequency and pass band ripple)
* the lowest frequency you want to attenuate and the minimum attenuation rate.
( = stop band frequency and stop band attenuation)
* filter impedance at passband

My recommendation.. if possible just use an analog filter that attenuates signals (amplitude of frequencies) above half_the_sampling_frequency to a uncritical value. The rest can be done in software more flexibly.

Information (mainly for first order filters):
An analog filter is not ideal. Calculating just with cutoff frequency (fc) of a filter (usually at -3dB) will give not satisfying results.
* The filter will not perfectly pass all signals up to fc, instead it sadly attenuates them. Close to fc the voltage value is just 70% (30% error). If you do power calculations then at cutoff you get 50% error.
* The filter will not perfectly attenuate frequencies above cutoff. Instead it starts at 70% of initial voltage and will drop just with 20dB per decade. This means at n × fc you just get 1/n of voltage. ( if you want to suppress frequencies of 10kHz to become just 1% of input amplitude then fc of the filter needs to be 1% of 10kHz = 100Hz)

If you want to improve the performance you have some options:
* use a higher order filter
* use a higher sampling rate and software filtering

Note: when an ADC input contains frequencies above f_sample/ 2 it will create alias frequencies in lower band.
Example: let's say your sampling frequency is 5000Hz and the "noise" is 4000Hz, then this will cause an alias frequency of 500Hz with the same amplitude as the 4000Hz.
You can't safely filter away alias frequencies on the digital side (software), thus you need to use an analog filter for this (anti aliasing filter)

Klaus

 

[danadakk]

Question, is your ADC Vref derived from Vdd or a bandgap ? If former
Vdd rail noise gets coupled into ADC measurement system, and extra
consideration should be given to Vdd filtering.

Not all caps, for equal C value, have the same ESR performance when
used in filtering. Pay attention to datasheet, even different manufacturers
for same technology have different ESR performance. Often used is a parallel
of two caps, one to handle bulk low freq stuff (tantalum) to one for high freq,
MLCC or Ceramic disk.

If your design can live with the latency of sample averaging that helps as
well. Some ap notes on that topic attached.

What is the processor being used ? Target accuracy and resolution ? Absolute or relative
accuracy needed ?


Regards, Dana.

 

[HighTechPower]

If your design can live with the latency of sample averaging that helps as
well. Some ap notes on that topic attached.

What is the processor being used ? Target accuracy and resolution ? Absolute or relative
accuracy needed ?


Regards, Dana.

Thank you Dana. I'm using PIC12F683. I want to do it without or little latency of sample averaging. I need instantaneous results instead of averaging. I had problem when using switch mode power source for the circuit. However I rectified the issue by using a 100 nF filter capacitor at the input of ADC but some time it still generate wrong results.

 

[danadakk]

Using internal or external Vref ?

If internal then Vdd is one issue to deal with. Take your scope, put it on infinite
persistence, and look at your supply rail. If your Vdd is 5V then 1 LSB =~ 5 mV, so
if Vdd rail noise, pk-pk, is 200 mV thats 40 lsb's of random error measuring full
scale.

You are adhering to ADC clock specifications.....?

If you supply a "clean" Vin of say 1/2 scale you still get noise out in readings ?
That indicates supply and layout issues. If no noise then when looking at actual
signal you have coupling issues into ADC, like C coupling adjacent pin logic
activity, long lead/traces picking up environmental stuff like fluorescent lights....
You could do a simple test code, all other HW shutoff, to either dismiss this as
an issue or work on it as a problem.....


Had a chance to look at Vin pin with a spectrum analyzer (lightly coupled) to
get clues of noise origin .....

It also helps in some chips to shut off other HW when doing a conversion, like
PWMs and other noise generating processes....

https://ww1.microchip.com/downloads/en/DeviceDoc/31023a.pdf

Keep in mind since you are single ended input any CM noise is a poroblem for you, that
includes coupled noise, noise due to ground bounce, etc....

I see this note in datasheet - The maximum recommended impedance for analog sources is 10 kΩ

Regards, Dana.

 

[HighTechPower]

Using internal or external Vref ?

You are adhering to ADC clock specifications.....?

If you supply a "clean" Vin of say 1/2 scale you still get noise out in readings ?

Regards, Dana.

Internal Vdd as Vref.

I was using FOSC/8 with 4 usec delay per sample generated by code using __delay_us(4) after GO_nDONE goes to zero in a while loop; where FOSC was 4 MHz.
ANSEL = 0b00010011;
------------------
ADCON0 = 0b10000100;
ADON = 1;
ADIF = 0;
GO_nDONE = 1;
while(GO_nDONE);
__delay_us(4);
adc = (((unsigned)ADRESH << 8) | ADRESL);

Also to mention that The normal voltage at ADC input was around 2.5 V and should not couple the lsb noise floor.

 

[KlausST]

Hi,

I see no benefit in using 4us delay after conversion is finished to read the result.
It won't improve anything.

On one hand you say you don't want latency by averaging ... on the other hand you cause much delay by using a 100nF.
From an engineer's view it doesn't make much sense. But it's not "wrong" either.
If you are satified with it, then leave it as it is. But if you need to optimize ... you may adjust here.

Klaus