An interview question? Is my answer right?

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there is a fifo design which the clock of data input is running at 100mhz,while the clock of data output is running at 80mhz. The input data is a fix pattern . 800 input clocks carry in 800 data continuously,and the other 200 clocks carry in no data.how big the fifo should be in order to avoid data over/under_run?please select the minimum depth below to meet the requirement.
A.160 B.200 C.800 D.1000

my answer is A. Is it right?
 

100Mhz is 10ns
80Mhz is 12.5ns

160 is correct.
 

worst case: 800 signal + 200 blank
input: 800 clk causes 800 signals
output: 800 clk causes 800*0.8=640 signals
the min FIFO buffer size = 800 - 640 = 160
 
for (800+200)*10ns = 10 000ns input passes 800 signals. Output passes 10 000/12.5 = 800 signals => this can work. Now, after sending 800 signals from input register, the fifo is full and starts to empty in next 200*10ns. While 800 signals were coming from input, output has taken 800*10ns/12.5ns=640 signals. Meaning, you need to store max 800-640=160 signals in FIFO.
 

the minimum size FIFO should contain the data come in 200 clocks, to have the read side have time to pop them up. so that the FIFO will not get overflow.
 

Hi,

time taken to fill 800bytes with 100Mhz clock is 8us.
Time taken to read single byte on the other side is .00125us
No. of bytes read in 8us is 640 bytes
so remaining byte count is the required buffer size i.e 800-640 = 160

So 160 is the correct answer.

Regards,
Kanags.
 

Well, I guess worst write can be as follows:

<-200-><-800->|<-800-><-200->
First burst | second burst

Then in this case fifo depth needs to be 320.
please, see the below link to know, how i derived it...


Am I Correct...???
Please, correct me if I am wrong.
 
Hi Bharat,


time taken to fill 800bytes with 100Mhz clock is 8us.
Time taken to read single byte on the other side is .00125us
No. of bytes read in 8us is 640 bytes
so remaining byte count is the required buffer size i.e 800-640 = 160

So 160 is the correct answer.

Peak buffer requirement will be at the end of 800bytes i.e completion of 800cycles write. The remaining 160bytes can be read in the period of remaining 200 write clock cycles. So at the end of 800 + 200 write clock cycles fifo will be empty and be available for next burst transfer.
 

Seems like i misinterpreted the problem...
"The input data is a fix pattern . 800 input clocks carry in 800 data continuously,and the other 200 clocks carry in no data. ".

I thought 200 ideal cycle can come at any time, at the start, in between or in the end.... But that is not the case.

@kanagavel_docs, you are right, in this case, as the input pattern is fix, the depth needed is only 160.

Anyways, thanks for correcting me...
 

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