library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;
entity testingmon is
port(clk :in std_logic;
hs : out std_logic;
vs : out std_logic;
red1 : out std_logic;
green2 : out std_logic;
reset :in std_logic;
blue2: out std_logic
);
end testingmon;
Architecture vga_arch of testingmon is
signal clkout : std_logic;
begin
process (clk,reset)
variable counter : integer :=1 ;
variable clktemp : std_logic:= '0';
begin
if(clk'event and clk ='1') then
if(counter /= 2) then
counter := counter + 1;
clkout <= clktemp;
elsif(counter =2) then
if(clktemp = '0')then
clktemp :='1';
counter := 1 ;
elsif(clktemp = '1') then
clktemp := '0';
counter := 1;
end if;
end if;
end if;
end process;
process(clkout,reset)
variable count: integer := 0;
variable vert : std_logic_vector (8 downto 0) := "000000000";
variable horiz :std_logic_vector (9 downto 0) := "0000000000";
begin
if(reset = '1') then
vert := "000000000";
horiz := "0000000000";
hs <= '0';
vs <='0';
blue2 <='0';
green2 <='0';
red1 <='0';
elsif(clkout'event and clkout ='1') then
if(vert = "111011111") then
vert := "000000000" ;
end if;
count := count +1;
if( count <= 96)then
if(count = 45) then
vert := vert + "000000001";
end if;
red1 <= '0';
green2<= '0';
blue2<= '0';
hs <= '0';
vs <= '1' ;
elsif(count>=97 and count <=144)then
hs <= '1';
vs<='0';
red1 <= '0';
green2<= '0';
blue2<= '0';
elsif(count >= 145 and count<=784) then
horiz := horiz + "0000000001";
hs <='1';
vs <='0';
red1 <= '1';
green2<= '1';
blue2<= '1';
elsif(count >=785 and count <= 800) then
horiz := "0000000000";
hs <='1';
vs <='0';
red1 <= '0';
green2<= '0';
blue2<= '0';
end if;
if(count = 800) then
count := 0;
end if;
end if;
end process;
end vga_arch;