An advice about glitch

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OvErFlO

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I have a FPGA Xilinx that generate a 20 Mhz clock (sclk) for drive a DAC, now when I trasmit serial data (sdata) from controller to DAC, DAC acquire serial datas on falling edge and on rising edge I observe glitch (I have see on modelsim simulation), the question is :

If I receive a glitch on rising edge, it's possible that my signal on falling edge can't obtain VIL or VOH to identify a 0 or a 1 ???

What can I do to avoid this ?

thanks
 

did you see glitch on the "real" hardware?
 

Hi,

First am not clear with the q i will reply with wat i undersatood.

glitches result when there is race condition or skew but on thing dude glitch can trigger the circuit and can take it on a metasatble state ride..

so it would be helpful if u get to root of the prob or explain i will try..

regards
 

A glitch is detrimental if it's on a clocking signal, as that can create an extra, unwanted clock period.

If it's on a "data" signal, it will be ignored if it occurs after the capturing clock edge, and it is stable long enough (satisfies setup time) before the next capturing clock edge.
 

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