I have a FPGA Xilinx that generate a 20 Mhz clock (sclk) for drive a DAC, now when I trasmit serial data (sdata) from controller to DAC, DAC acquire serial datas on falling edge and on rising edge I observe glitch (I have see on modelsim simulation), the question is :
If I receive a glitch on rising edge, it's possible that my signal on falling edge can't obtain VIL or VOH to identify a 0 or a 1 ???
A glitch is detrimental if it's on a clocking signal, as that can create an extra, unwanted clock period.
If it's on a "data" signal, it will be ignored if it occurs after the capturing clock edge, and it is stable long enough (satisfies setup time) before the next capturing clock edge.