AMS .35 HV process Layout Issue

[mvj]

Dear All,

I am working on the layout of my circuit and I am having a problem which I am not able to resolve, can you please help me out.

When I run DRC I get the below mentioned error though the gate terminals are connected to a pin.
[1] ERCWarning: floating gate not connected to s/d, pad, pin or resistor.


To reproduce this problem, i have taken a trasistor and connected pins to all the terminals of the device. At the gate terminal, I connected a poly to M1 contact, then VIA1, M2 Track and M2 pin (images attached for you reference). I have checked it throughly but I am not to resolve this problem. Can you please help me out.


Thanks a lot in advance!!



Best Regards,
M.

 

[dgnani]

hi mvj
if LVS is clean I would not bother with an ERC issue flagged by DRC, chances are that it is miscoded

 

[erikl]

... error though the gate terminals are connected to a pin.
[1] ERCWarning: floating gate not connected to s/d, pad, pin or resistor.
...
At the gate terminal, I connected a poly to M1 contact, then VIA1, M2 Track and M2 pin ...

Did you also use the MET2 pin layer?

 

[dgnani]

Did you also use the MET2 pin layer?

I don't know about Assura but for Calibre the port stamping layer is PIN:metal2 (abbreviated PIN:M2 in LSW) not MET2in; for example the latter is not exported to gds...

 

[AdvaRes]

Hi,
Your prb is an ERC and not a DRC probkem.

 

[mvj]

I got the problem resolved.

I placed a pin ( ctrl + p). This is ok for DIVA and not for Assura. In Assura a layer of type PIN:M2 should be placed as mentioned by dgnani.

Thank you for your help!!