Hello everybody,
i am new in Hardware design have a project in designing an AXI Bus in VHDL and testbench in SystemC (Co-verification). I read some documentation and have understood how it works, now could some experienced persons tell me which are the steps i should follow, for example what are the different VHDL entities i will need (Channels, Decoder, Arbiter...)
my next question is the following:
must i design the bridge to the low speed slaves myself? and what about the APB?
If you have sample code (verilog is also welcome), please share with me.
Thanks