Alu Circuit Design & state diagram

[abukharmeh]

Hello,
i have to design 32 bit alu unit that do normal unsigned multiplication, booths multiplication and unsigned division

In binary format, i know that we multiply lsb by of the one number by the other number
and then we save the result in some register , and then we get the bit next to the lsb we multiply and shift the result one bit to the left and we add it to the previous result we got, and continue doing that till we finish from all the bits, thats what i know for the first op, and like wise i know how the second and the third operate,

but the problem is that i cant imagine the logic circuit doing so, like shift register , and registers and so on, i need help of how to do this

And we are also asked to design the our fsm after finishing with d type flip flops, what are the use of the flip flop here, are they for the control of circuit, like when op code, the FSM will jump to some chunk of the digital circuit, or there is any use of them to do the operations

Is there any recommendation of software that can be used to simulate and build the circuit to understand how it act, preferably under linux, i am currently trying to use logisim but cant get how the connections are made, is there any place i can find an alu design in logisim so i can build on it

In the case of ALU, what could be expected to be the state diagram, currently i have IDLE state at the very top, then three branches to three states one is MUL, the other is booths and the third is DIV, but i have been told that there is around 8 remaining states after thoose what could be they


Any help, what ever its is would be great

Thanks.

 

[robmar]

Regarding the number of states I don't believe there is a fixed number of states that the FSM should be comprised of. Try to model the whole FSM with as many states as you want and then go over it again removing redundant states or merging identical ones.

For a simulation you could write your circuit in VHDL/Verilog and use softwares likes Altera Quartus/Xilinx Vivado/Design Compiler+ModelSim (or any other simulator). These tools give you the possibility to analyze many details of your design. Perhaps try to start with a behavioral approach and then try a structural one like you have mentioned.

Hope this helps

 

[abukharmeh]

Regarding the number of states I don't believe there is a fixed number of states that the FSM should be comprised of. Try to model the whole FSM with as many states as you want and then go over it again removing redundant states or merging identical ones.

For a simulation you could write your circuit in VHDL/Verilog and use softwares likes Altera Quartus/Xilinx Vivado/Design Compiler+ModelSim (or any other simulator). These tools give you the possibility to analyze many details of your design. Perhaps try to start with a behavioral approach and then try a structural one like you have mentioned.

Hope this helps

Thank you very much, i have installed Altera Quartus, and found some verilog module that does what i am trying to make, however i am trying to call these module from my top module and i am unable to make it work, i am novice in verilog and thats the code i manged to put together till now

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Code Verilog - [expand]
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module top (
clock      , 
reset      , 
numa            ,
numb            ,
opcode      ,
result         
);
 
input   clock,reset,opcode;
input numa,numb;
output result;
wire    clock,reset,opcode;
 
//parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
 
 
generate 
always @ (posedge clock)
 if(opcode == 2'b00)
        u_mult multi(result,numa,numb);
 else if(opcode == 2'b01)
         u_mult u_booths_mul(result,ready,numb,numa,start,clock);
 else if (opcode == 2'b02') 
         u_mult u_divide(quotient,remainder,ready,numa,numb,start,clock);
 else
 endgenerate
         
endmodule 
 
module u_mult(product,multiplier,multiplicand); 
   input [15:0]  multiplier, multiplicand;
   output        product;
 
   reg [31:0]    product;
 
   integer       i;
 
   always @( multiplier or multiplicand )
     begin
        product = 0;
 
        for (i=0; i<16; i=i+1)
          if ( multiplier[i] == 1'b1 )
            product = product + ( multiplicand << i );
        end
 
endmodule
 
 
module u_booths_mul(product,ready,multiplicand,multiplier,start,clk);
 
   input [15:0]  multiplicand, multiplier;
   input         start, clk;
   output        product;
   output        ready;
 
   reg [31:0]    product;
 
   reg [4:0]     bit;
   wire          ready = !bit;
 
   initial bit = 0;
 
   wire [17:0]   multiplicand_X_1 = {2'b0,multiplicand};
   wire [17:0]   multiplicand_X_2 = {1'b0,multiplicand,1'b0};
   wire [17:0]   multiplicand_X_3 = multiplicand_X_2 + multiplicand_X_1;
 
   always @( posedge clk )
 
     if ( ready && start ) begin
 
        bit     = 8;
        product = { 16'd0, multiplier };
 
     end else if ( bit ) begin:A
 
        reg [17:0]    pp;  // Partial Product
        reg [1:0]     mb;  // Multiplier Bits
 
        mb = product[1:0];
 
        case ( mb )
          2'd0: pp = {2'b0, product[31:16] };
          2'd1: pp = {2'b0, product[31:16] } + multiplicand_X_1;
          2'd2: pp = {2'b0, product[31:16] } + multiplicand_X_2;
          2'd3: pp = {2'b0, product[31:16] } + multiplicand_X_3;
        endcase
 
        product = { pp, product[15:2] };
        bit     = bit - 1;
 
     end
 
endmodule
 
module u_divide(quotient,remainder,ready,dividend,divider,start,clk);
 
   input [15:0]  dividend,divider;
   input         start, clk;
   output [15:0] quotient,remainder;
   output        ready;
 
   reg [15:0]    quotient;
   reg [31:0]    dividend_copy, divider_copy, diff;
   wire [15:0]   remainder = dividend_copy[15:0];
 
   reg [4:0]     bit;
   wire          ready = !bit;
 
   initial bit = 0;
 
   always @( posedge clk )
 
     if ( ready && start ) begin
 
        bit = 16;
        quotient = 0;
        dividend_copy = {16'd0,dividend};
        divider_copy = {1'b0,divider,15'd0};
 
     end else begin
 
        diff = dividend_copy - divider_copy;
        quotient = { quotient[14:0], ~diff[31] };
        divider_copy = { 1'b0, divider_copy[31:1] };
        if ( !diff[31] ) dividend_copy = diff;
        bit = bit - 1;
 
     end
 
endmodule

---

 

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Re: Alu Circuit Design & state diagram

---

Code Verilog - [expand]
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generate 
always @ (posedge clock)
 if(opcode == 2'b00)
        u_mult multi(result,numa,numb);
 else if(opcode == 2'b01)
         u_mult u_booths_mul(result,ready,numb,numa,start,clock);
 else if (opcode == 2'b02') 
         u_mult u_divide(quotient,remainder,ready,numa,numb,start,clock);
 else
 endgenerate

---

This code implies that the modules are instantiated by the clock depending on the current state of the opcode. This is impossible, hardware always exists in a design there is no such thing as dynamically linked hardware (i.e. the equivalent of a dynamical link library). You don't call instantiated modules, you instantiate a module then you would select how the wires interconnect things (i.e. multiplexers, demultiplexers).

Also never use positional port mapping, instead used named association port mapping.

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Code Verilog - [expand]
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// No!, never use this style, and are you a VHDL user? (you have the instance name before the module name)
u_mult multi(result,numa,numb);
// this connects the multi module like this:
//   result = multiplier
//   numa = multiplicand
//   numb = product
// which I assume is the wrong hookup!
 
// Use the named association style
multi  u_mult (
  .product       (result),
  .muliplier     (numa),
  .multiplicand  (numb)
);

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- - - Updated - - -

Also use Verilog 2001 syntax for module port declarations, using the antiquated style is redundant and a waste of time and is more prone to having errors.