davorin
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altsyncram
Anybody experienced same bus as Quartus II 4.1 synthesizes away declared ROM blocks with init-file?
I have 3 identical ROM blocks with each having its own MIF init file:
But only 1 ROM block is synthesized no matter what I do....though all 3 are using same inputs and outputs are driving VGA port...
Anybody experienced same bus as Quartus II 4.1 synthesizes away declared ROM blocks with init-file?
I have 3 identical ROM blocks with each having its own MIF init file:
Code:
rom1 red(
.address({back[9:0],tile_delta}),
.clock(~horizontal[2]),
.q(tiles_c)
);
rom2 green(
.address({back[9:0],tile_delta}),
.clock(~horizontal[2]),
.q(tiles_b)
);
rom3 blue(
.address({back[9:0],tile_delta}),
.clock(~horizontal[2]),
.q(tiles_a)
);But only 1 ROM block is synthesized no matter what I do....though all 3 are using same inputs and outputs are driving VGA port...