Altium Signal Integrity - defaults to 5V

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Jester

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It seems that Altium assumes a default 5V for Vcc when performing signal integrity. I have added a directive for GND (0 Vdc) as well as VCC (3.3Vdc) on the schematic and these appear in the PCB signal integrity design rules, however the reflection plots default to VCC = 5.0V as shown below. I'm still waiting for the IBIS model (can't find it on the Freescale website) so until I get it I'm using the default HC model in Altium.

Is there a global setting for the Altium HC model that I can change from 5.0V to 3.3Vdc?

 

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