altium does create a room for the middle sheet, but it only contains the ics and two caps, so I'm not sure the best way of getting from that (bottom part of attached fig) to what I want, where the routing is all complete (the top part of attached fig). It seems I can't do this if I leave them as separate rooms.
If I delete all the small rooms, as I have done, and draw a new room around the middle and lower sheets, nothing will match by channel offset. I suppose this is because they all have conflicting channel offsets - all components are named either 1,2,3,4. If I match by source designator, the ICs will match and place but only one of the small rooms is placed properly. I suppose this is because as the ICs have only one version they will match but again, all the designators for the smaller rooms are somehow conflicting.
I suppose there is a way of altering how the designators for the small rooms are generated which might mean that this would work, but I don't fully understand how copy room formats uses the designators to match