Alternative for VHDL 2008 "alias"

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dpaul

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I am using the VHDL 2008 alias and it functions perfectly with Modelsim DE 10.2 64bit.
alias ddr3_ready is <<signal dp_top_inst.amba_sys_inst.ddr3_ready_o : std_logic>>;

Since the number of licenses are limited, so not everyone in our team has access to it at the same time.

At a given time, if all licenses are in use, then me or my colleagues use the default Microsemi Modelsim version that comes bundled with Microsemi Libero SoC dev tool.
The problem starts now. This Microsemi Modelsim version has a problem working with alias. Following is the compilation error I get.

** Error (suppressible): (vsim-FLI-3155) The FLI is not enabled in this version of ModelSim.

What can be a suitable workaround in this scenario?

Well I can tell my testbench to wait for z.y usec until the ddr3_ready_o signal goes high. Any better solutions other than this?
 

What language is the amba_sys_inst written in? FLI is the foreign language interface. Are you doing an external name into non-VHDL code? if thats the case, then theres no real work around.
 

Well the amba_sys is a Microsemi block design, and the Libero SoC tool generates a vhdl wrapper for it. This vhd wrapper is instantiated inside my top level.
 

Alias itself is not a 2008 feature - its been around since VHDL 87. The 2008 thing here is the external name inside << >> . I suspect that whever you're using as an external name is not VHDL, hence the enhanced licencing required. The only other option really is to route the signal into the testbench through port maps to access it.
 

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