Hi,
I have to design a sequential circuit which is used to detect clock edges alternately, i.e. the even edges should be in an output and odd edges in an output as shown in fig... Can any one suggest me a design to get the output..
D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).
Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.
D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).
Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.
Thank you Dan :smile: , I got what you suggested. There are glitches as you mentioned. I need this output for a Duty Cycle corrector and I think it's better to avoid the glitches. Is there any way to remove the glitches?? Any how the output looks like this