Alternate clock edge detection

Dan Mills said:

Rising edge triggered D type and two and gates?

D type wired as a divide by two with the Q and *Q outputs anded with the clock to give even and odd outputs that are the same width as the clock (There might be a slight glitch due to the prop. delay of the D type).

Nick deans circuit does not match the clock timing and in any case if that is all that is required a simple D type /2 is very much easier.

Regards, Dan.

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Dan Mills said:

Google "d type divide by two", it is about as simple as it gets.

Dan.

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