Altera router estimated peak interconnect usage is above 100% in some areas

Hi,
I am having trouble synthesizing RTL using quartus.
I get the error at the end of my message and routing fails which seems to be because of this. The interconnect usage is above 100% in some areas.
I switched from Stratix 4 to 5 and also a to a bigger device and still see the problem.
Some people suggested me to use logiclock. That didn't help me. Logiclock defines an area for a block but it doesn't force Quartus to use all the area.
I need to spread the design in bigger area so that the FLOPS are in wider area and the routing is not too congested.

Is there any way to ask quartus to put more distance between LUTs (or FLOPS)?

Any help is appreciated.
I am using quartus II 64 bit version 13.0.1 full version. The device is Stratix 4.
Using different seed doesn't help.

Thanks
Alex


Info (170195): Router estimated average interconnect usage is 23% of the available device resources
Info (170196): Router estimated peak interconnect usage is 104% of the available device resources in the region that extends from location X162_Y23 to location X173_Y34

Try creating logic lock regions inside the other region and exclude logic from being placed there. Perhaps a couple of columns and rows. That will force the placer to not pack everything as close to each other.

Regards

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You might also consider playing around with the synthesis settings. Like reducing the effort and enabling things like register balancing.

is the congestion happening in a single entity or multiple entities? using the logic locks you can force the entities into two (or more) separate regions. but obviously this may hurt timing.

Do you also have some aggresive timing specs on the design? lots of async logic, or logic between flops?

Synthesis takes two inputs: constraints and code. The first step is to determine which is the problem.

If you have existing constraints then try removing them all (leaving only the chosen part that you want) and just let Quartus synthesize the design. If it routes, then you should start to suspect the constraints that you removed.

If the problem is not existing constraints, then the problem must be with your code. First thing would be to locate which logic is being implemented at the locations of high interconnect using the netlist viewer and track that back to at least a general area of your code. Once you have that you'll have to put your thinking cap on to see if there is another way to implement your function. Using the netlist viewer to get an idea of how your code is translated into actual hardware might help but expect that it could be a tedious task until you get to the 'ah ha' moment.

Trying to leap to a solution such as wanting to put more distance between used LUTs is pointless if you don't understand the root cause problem. In addition to the informational message that you posted, there must have been some actual error message when the routing failed. There is possibly a clue in there.

Kevin Jennings