Altera RAM "pass-through logic" warning?

 data2cpu <= memory[mem_addr];
 if (wea) begin
  data2cpu <= tmp_mem;
  memory[mem_addr] <= tmp_mem;
 end

module inram_controller(
 input rst,
 input clk,
 input os_write_lock,

 input  [31:0] addr,
 input  [31:0] data2mem,
 output reg [31:0] data2cpu,
 input  re,
 input  we,
 output reg done
);

wire p=re|we;
reg [9:0] mem_addr;
reg [1:0] state;
reg [31:0] tmp_mem;

parameter [1:0] inram_idle = 2'd0;
parameter [1:0] inram_op   = 2'd1;
parameter [1:0] inram_skip = 2'd2;

reg [31:0] memory[1023:0]; //1024*4=4kb
integer n;

initial begin
 for (n = 0; n < 1024; n = n + 1) memory[n] = 0;
 
 memory[0] = 32'h0B0B0B0B;
 memory[1] = 32'h80A00894;
 memory[2] = 32'h0B0C0A81;
 memory[3] = 32'h800B0B0B;
 memory[4] = 32'h00000004;
 memory[5] = 32'hFFFFFFFF;
end

always @(posedge clk)
begin 
 if (rst) begin 
  //$display("inram_reset");
  state <= inram_idle;
  data2cpu <= 0;
  done <= 0;
  mem_addr <= 0;
 end else begin
  case (state)
   inram_idle: begin
    //$display("inram_idle: we=%d, re=%d", we, re);
    done <= 0;
    if (p) begin
     state <= inram_op;
     mem_addr <=a ddr[11:2];
     tmp_mem <= data2mem;
    end
   end
   inram_op: begin
    $display("inram_op: %d(%d), we=%d, re=%d", addr, mem_addr, we, re);
    if (we) memory[mem_addr] <= tmp_mem;
    else if (re) data2cpu <= memory[mem_addr];
    done <= 1;
    state <= inram_skip;
   end
   inram_skip: begin
    done <= 0;
    state <= inram_idle;
    mem_addr <= 0;
   end
  endcase
 end
end

endmodule

Warning: Inferred RAM node "inram_controller:inramc|memory_rtl_0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.

    Info: Inferred altsyncram megafunction from the following design logic: "inram_controller:inramc|memory_rtl_0" 
        Info: Parameter OPERATION_MODE set to DUAL_PORT
        Info: Parameter WIDTH_A set to 32
        Info: Parameter WIDTHAD_A set to 10
        Info: Parameter NUMWORDS_A set to 1024
        Info: Parameter WIDTH_B set to 32
        Info: Parameter WIDTHAD_B set to 10
        Info: Parameter NUMWORDS_B set to 1024
        Info: Parameter ADDRESS_ACLR_A set to NONE
        Info: Parameter OUTDATA_REG_B set to UNREGISTERED
        Info: Parameter ADDRESS_ACLR_B set to NONE
        Info: Parameter OUTDATA_ACLR_B set to NONE
        Info: Parameter ADDRESS_REG_B set to CLOCK0
        Info: Parameter INDATA_ACLR_A set to NONE
        Info: Parameter WRCONTROL_ACLR_A set to NONE
        Info: Parameter INIT_FILE set to db/ep_test.ram0_inram_controller_8b3d01f9.hdl.mif
        Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA

    if (we) memory[mem_addr] <= tmp_mem;
    else if (re) data2cpu <= memory[mem_addr];

  case (state)
   inram_idle: begin
    done <= 0;
    if(p) begin
     mem_addr <= addr[11:2];
     if (we) state <= inram_wr;
     if (re) state <= inram_rd;
    end
   end
   inram_rd: begin
    data2cpu <= memory[mem_addr];
    done <= 1;
    state <= inram_skip;
   end
   inram_wr: begin
    memory[mem_addr] <= data2mem;
    done <= 1;
    state <= inram_skip;
   end
   inram_skip: begin
    done <= 0;
    state <= inram_idle;
    mem_addr <= 0;
   end
  endcase