jayvijay
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Hi friends !!!! ...
Objective :
To downsample a 110 MHZ samples to 40 MHz using Altera FIR Compiler IP core ...
Method :
I/P rate = 110 MSPS
Clk rate =220 MHz
O/p rate =40 MSPS
I am unable to go with 440 MHZ clk eventhough I will get output for every 11 clocks (440/40=11)as stratixV will accept only 400 MHz as max....
Questions :
1. Is there any other method to do downsample with clk matching both input & output rates ... ?
2.Is my way of calculation right .... ?
regards
jayvijay
Objective :
To downsample a 110 MHZ samples to 40 MHz using Altera FIR Compiler IP core ...
Method :
I/P rate = 110 MSPS
Clk rate =220 MHz
O/p rate =40 MSPS
I am unable to go with 440 MHZ clk eventhough I will get output for every 11 clocks (440/40=11)as stratixV will accept only 400 MHz as max....
Questions :
1. Is there any other method to do downsample with clk matching both input & output rates ... ?
2.Is my way of calculation right .... ?
regards
jayvijay