emrelevent
Newbie level 1
- Joined
- Jan 13, 2013
- Messages
- 1
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,287
I have problem with pci express avalon busses. Altera's ip core has may input output on generated module. I didnt figure out how to drive all those io.
My board has following pci express signals,
PCIE_PERST_N PCIE_REFCLK_P PCIE_RX_P PCIE_TX_P PCIE_WAKE_N
And i only need tx_en, tx_data, tx_busy, rx_en,rx_data.
How can i wrap qsys generated module?
Thanks.
My board has following pci express signals,
PCIE_PERST_N PCIE_REFCLK_P PCIE_RX_P PCIE_TX_P PCIE_WAKE_N
And i only need tx_en, tx_data, tx_busy, rx_en,rx_data.
How can i wrap qsys generated module?
Thanks.