The way I translate your post:
"I did something, or maybe I did not do something. This process results in a .sof file. When I program that .sof file to the fpga the programming in itself is succesful, but the design does not do what I want. When I program an older .sof from somewhere this also programs succesfully, and as a bonus the led goes blinkie. A coworker also does something that creates a .sof file, and that also makes things blink."
That leads me to conclude that the "program fpga with .sof file" part works, which is good.
You also have an old .sof somewhere that does what you want. So at some point in time your design was okay, and the synth + PAR tools were able to create a working .sof file.
Only now for whatever reason the latest .sof doesn't work. This could be because your current design is incorrect. It could also be that the design is correct (because of course it is, and you did not make any changes. noone ever does
) but there are some intermediate files that mess things up.
Possible solution:
- clean project ==> all intermediate files so be removed.
- rerun everything from synthesis to place & route and generate .sof file
- check date stamps of files to make damn sure you have the right one
- retry the new .sof file
- profit?
If that does NOT work, give your latest FULL project to your coworker and let him run the above on his machine. If that suddenly results in things working then you have a problem. But I suspect the results will be the same for both machines.
Anyways, far too long, but I hope it helps.