Altera DE2-115 SDRAM byte enables

[hexaeder]

I've made an SDRAM controller unit in Verilog for Altera DE2-115 but it seems that the byte enable signals DRAM_DQM[3:0] do not actually do anything, at least on my board. Regardless whether they're set high or low, the writes and reads result in a 32 bit write or read even though they are connected to the pins defined in the DE2-115 manual. Has anyone gotten the byte enables to work with the SDRAM in DE2-115?

 

[FvM]

What are you exactly observing? DQM lines aren't operated by the controller as expected or are operated but have apparently not the expected effect?

Expected DQM timing can be reviewed in SDRAM datasheet. Although they can be used to put DQ outputs in high Z on read operation, the relevant usage is typically write enable for byte oriented data. Therefore the design must not necessarily operate DQM during read, just keep it low.

 

[hexaeder]

What are you exactly observing? DQM lines aren't operated by the controller as expected or are operated but have apparently not the expected effect?

Expected DQM timing can be reviewed in SDRAM datasheet. Although they can be used to put DQ outputs in high Z on read operation, the relevant usage is typically write enable for byte oriented data. Therefore the design must not necessarily operate DQM during read, just keep it low.

My controller sets the DQM lines but there doesn't seem to be any effect to neither writes nor reads. Regardless whether the controller sets them high or low or any combination of them, the writes will always write all 32 bits to SDRAM, and reads will always return a value where none of the bytes have been masked off. Judging by the datasheet, DQM should be set three cycles before any write, and my controller implements it as such.

Even if the DQM lines are forced to be constantly high or low has no effect.

 

[FvM]

DQM function according to Micron SDRAM datasheet:

Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered LOW, the corresponding DQs will provide valid data.

Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location.

 

[hexaeder]

DQM function according to Micron SDRAM datasheet:

If I understood correctly, the DQM needs to be set three cycles before when doing burst. But as said, forcing the DQM signals *always* to be either high or low, has no effect on neither reads nor writes. On writes, all bytes are written, on reads, all bytes are read and they never show High-Z regardless of what is being fed into DQM.