Altera Cyclone IV FPGA SPI

[I_THINK_ITS_SHORTED]

I'm having some trouble getting serial SRAM to work using the Altera DE2-115. I tried using the "SPI (3 Wire Serial)" IP core, but after mapping the exported signals to the GPIO pins I can't seem to properly control the memory. I'm also not sure if its a problem that the SRAM is 4 wire SPI, since all 4 necessary signals are present in the "3 wire" serial IP core.

I suspect my problem has to do with my Qsys setup, specifically the connections between the SPI components, as shown below.

Not sure how I should be configuring the connections for a simple 4 wire SPI. I tried just the 3 wire component on its own but that didn't seem to work, however that may have been the fault of my code. The documentation has me thinking that the bridge might be required for memory mapped access to the SPI, but I'm not sure of that either. Thanks in advance for any help offered.

 

[FvM]

How dow you test the SRAM, how do you see it's not working? Did you monitor the SPI lines with Signaltap?

--- Updated Feb 13, 2022 ---

What's the purpose of the SPI slave bridge in your design?

 

[I_THINK_ITS_SHORTED]

I monitored the lines using signaltap and the result makes me think the SPI 3-wire controller can only be used for 3-wire SPI and not 4. Basically MOSI and MISO both go high simultaneously during a byte transfer. The SRAM I'm using requires separate in and out lines, not one bidirectional line, so this might be the problem.

As for the bridge, I added it thinking that maybe I was missing some logic between the SPI and FPGA that allowed the SPI to be memory mapped, which I now think was incorrect.

I think my problem is configuring Qsys for a 4-wire SPI, not 3.

 

[FvM]

I believe the 3 wire thing is a misunderstanding. SPI core has always 4 wires, separate MOSI and MOSI lines. Review embedded peripherals IP user guide. Did you connect MISO line corretly to serial SRAM?

 

[I_THINK_ITS_SHORTED]

I double checked the wire connections and they are all correct.

 

[FvM]

If so, who or what is driving the MISO signal in your signaltap?

 

[I_THINK_ITS_SHORTED]

I'm not sure what the correlation is but in my test code I am using "alt_avalon_spi_command" for general read and write from the SPI. I changed the flag value parameter in the function to "ALT_AVALON_SPI_COMMAND_MERGE" and this fixed the problem of the MISO signal mimicking the MOSI.

The MISO now remains in a state of high impedance during MOSI output, which is the desired behavior for the SRAM.

Looks like the problem was my code, I should be able to get it working now. Thanks for your help, didn't even know signaltap existed. Very useful.