Allowable skew of data bus lines

[shaiko]

Suppose a processor is communicating with an external RAM via a parallel bus @ 100MHz.
What is the maximum allowable timing skew between 2 data bits on that bus?

 

[FvM]

No specific limit. RAM setup- and hold requirements must be met, bus timing will be programmed respectively.

 

[ro9ty]

There will not be limit on the skew separately but when you will calculate for the setup and hold and ensure that there is no violation then you will use the clock period (propagated) Hence, the skew would be adjusted in it.

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There will not be limit on the skew separately but when you will calculate for the setup and hold and ensure that there is no violation then you will use the clock period (propagated) Hence, the skew would be adjusted in it.[/ Did you find this post helpful? Click: Yes]