valeriogiampa
Member level 3
Hi,
I have two boards (one in FR4 and one in roger) connected to each other by two Samtec connectors.
I have all models necessary for the SI simulation (transmitters, receivers, ferrite bead and connectors samtec).
I have done correctly (I assume) the setup of the models.
Allegro PCB SI is able to extrapolate correctly the topology of the net that I want to analyze, but it is not able to run the simulation.
I have observed that to removing the connector in SigXplorer, the simulation starts without problems.
The model that I was using for the connector is DS_ftshdv_clp_end.dml (Samtec).
Also, I have used the Cadence Application Note (Modeling Connectors in ESPICE Format for Use in SigXplorer: Application Note).
I wanted to know if you can help me to solve this problem to use the samtec connector espice models for this simulation.
The Basic Signal Integrity Model for reflection analisys of the Samtec:
("DS_ftshdv_clp_end.dml"
(PackagedDevice
("FTSHDVCLPEL"
(ESpice ".SUBCKT FTSHDVCLPEL 1 2
**************************************IN*OUT
********************************************
** REV 1.0 12/14/04 **
** THIS SUBCIRCUIT IS FOR THE END PINS OF **
** THE CLP Series 5.13mm MATED CONNECTOR **
** **
********************************************
********************* END ******************
********************************************
T4 1 0 2 0 Z0=66 TD=25PS
.ENDS FTSHDVCLPEL
** END OF END PIN T-LINE SUBCIRCUIT **
********************************************
")
(PinConnections
("1" "2")
("2" "1"))
(XNetConnections
("1" "2")
("2" "1")))))
;******Modified by Cadence Design Systems*****
;[dmlcheck v16-3-85D]
; EXECUTED_AT= Mon March 18 10:51:48 2013
; FILE_MOD_TIME= Mon May 22 09:14:48 2006
; RESULT= 0 errors, 0 warnings
; OPTIONS= -ab
;***End Cadence Design Systems Modification***
To adapt the model for all pin of the connector, I have changed the previous model with this model:
("FPS5220.dml"
(PackagedDevice
("FPS5220"
(ESpice ".subckt FPS5220 1 n1 2 n2 3 n3 4 n4 5 n5 6 n6 7 n7 8 n8 9 n9 10 n10 11 n11 12 n12 13 n13 14 n14 15 n15 16 n16 17 n17 18 n18 19 n19 20 n20 21 n21 22 n22 23 n23 24 n24 25 n25 26 n26 27 n27 28 n28 29 n29 30 n30 31 n31 32 n32 33 n33 34 n34 35 n35 36 n36 37 n37 38 n38 39 n39 40 n40
.param Rc=0.025
R1 1 n1 'Rc'
R2 2 n2 'Rc'
R3 3 n3 'Rc'
R4 4 n4 'Rc'
R5 5 n5 'Rc'
R6 6 n6 'Rc'
R7 7 n7 'Rc'
R8 8 n8 'Rc'
R9 9 n9 'Rc'
R10 10 n10 'Rc'
R11 11 n11 'Rc'
R12 12 n12 'Rc'
R13 13 n13 'Rc'
R14 14 n14 'Rc'
R15 15 n15 'Rc'
R16 16 n16 'Rc'
R17 17 n17 'Rc'
R18 18 n18 'Rc'
R19 19 n19 'Rc'
R20 20 n20 'Rc'
R21 21 n21 'Rc'
R22 22 n22 'Rc'
R23 23 n23 'Rc'
R24 24 n24 'Rc'
R25 25 n25 'Rc'
R26 26 n26 'Rc'
R27 27 n27 'Rc'
R28 28 n28 'Rc'
R29 29 n29 'Rc'
R30 30 n30 'Rc'
R31 31 n31 'Rc'
R32 32 n32 'Rc'
R33 33 n33 'Rc'
R34 34 n34 'Rc'
R35 35 n35 'Rc'
R36 36 n36 'Rc'
R37 37 n37 'Rc'
R38 38 n38 'Rc'
R39 39 n39 'Rc'
R40 40 n40 'Rc'
.ends FPS5220 ")
(PinConnections
(1 n1) (n1 1)
(2 n2) (n2 3)
(4 n4) (n4 4)
(5 n5) (n5 5)
(6 n6) (n6 6)
(7 n7) (n7 7)
(8 n8) (n8 8)
(9 n9) (n9 9)
(10 n10) (n10 10)
(11 n11) (n11 11)
(12 n12) (n12 12)
(13 n13) (n13 13)
(14 n14) (n14 14)
(15 n15) (n15 15)
(16 n16) (n16 16)
(17 n17) (n17 17)
(18 n18) (n18 18)
(19 n19) (n19 19)
(20 n20) (n20 20)
(21 n21) (n21 21)
(22 n22) (n22 22)
(23 n23) (n23 23)
(24 n24) (n24 24)
(25 n25) (n25 25)
(26 n26) (n26 26)
(27 n27) (n27 27)
(28 n28) (n28 28)
(29 n29) (n29 29)
(30 n30) (n30 30)
(31 n31) (n31 31)
(32 n32) (n32 32)
(33 n33) (n33 33)
(34 n34) (n34 34)
(35 n35) (n35 35)
(36 n36) (n36 36)
(37 n37) (n37 37)
(38 n38) (n38 38)
(39 n39) (n39 39)
(40 n40) (n40 40))
(XNetConnections
(1 n1) (n1 1)
(2 n2) (n2 3)
(4 n4) (n4 4)
(5 n5) (n5 5)
(6 n6) (n6 6)
(7 n7) (n7 7)
(8 n8) (n8 8)
(9 n9) (n9 9)
(10 n10) (n10 10)
(11 n11) (n11 11)
(12 n12) (n12 12)
(13 n13) (n13 13)
(14 n14) (n14 14)
(15 n15) (n15 15)
(16 n16) (n16 16)
(17 n17) (n17 17)
(18 n18) (n18 18)
(19 n19) (n19 19)
(20 n20) (n20 20)
(21 n21) (n21 21)
(22 n22) (n22 22)
(23 n23) (n23 23)
(24 n24) (n24 24)
(25 n25) (n25 25)
(26 n26) (n26 26)
(27 n27) (n27 27)
(28 n28) (n28 28)
(29 n29) (n29 29)
(30 n30) (n30 30)
(31 n31) (n31 31)
(32 n32) (n32 32)
(33 n33) (n33 33)
(34 n34) (n34 34)
(35 n35) (n35 35)
(36 n36) (n36 36)
(37 n37) (n37 37)
(38 n38) (n38 38)
(39 n39) (n39 39)
(40 n40) (n40 40))
)))
;******Modified by Cadence Design Systems*****
;[dmlcheck v16-3-85D]
; EXECUTED_AT= Mon March 18 13:54:28 2013
; FILE_MOD_TIME= Mon Mar 18 13:54:25 2013
; RESULT= 0 errors, 0 warnings
; OPTIONS= -ab
;***End Cadence Design Systems Modification***
The element used for all pin in this case is a resistor RC but I have used also the Transmission line. The pins 1...40 are the internal pin of the connector, while the pins n1..n40 are the external pins of the connector.
The log file of the simulator point this message:
**** Tlsim Version 16.2 ****
**** Tlsim command line ****
tlsim -r 1.250000 -o waveforms.sim -dl delay.dl -dst distortion.dst -log tlsim.log -ocycle cycle.msm main.spc
*********************************************************
ABORT: Check your reference to Sckt FPS5220
*********************************************************
*********************************************************
ABORT: Unable to Compile SubCircuit 'FPS5220'
*********************************************************
**** Tlsim Run Times ****
Start time = Thu Mar 21 09:15:18 2013
Finish time = Thu Mar 21 09:15:19 2013
Elapsed time = 0 hours, 0 minutes, and 1 seconds
Can anyone suggest me a solution?
I have two boards (one in FR4 and one in roger) connected to each other by two Samtec connectors.
I have all models necessary for the SI simulation (transmitters, receivers, ferrite bead and connectors samtec).
I have done correctly (I assume) the setup of the models.
Allegro PCB SI is able to extrapolate correctly the topology of the net that I want to analyze, but it is not able to run the simulation.
I have observed that to removing the connector in SigXplorer, the simulation starts without problems.
The model that I was using for the connector is DS_ftshdv_clp_end.dml (Samtec).
Also, I have used the Cadence Application Note (Modeling Connectors in ESPICE Format for Use in SigXplorer: Application Note).
I wanted to know if you can help me to solve this problem to use the samtec connector espice models for this simulation.
The Basic Signal Integrity Model for reflection analisys of the Samtec:
("DS_ftshdv_clp_end.dml"
(PackagedDevice
("FTSHDVCLPEL"
(ESpice ".SUBCKT FTSHDVCLPEL 1 2
**************************************IN*OUT
********************************************
** REV 1.0 12/14/04 **
** THIS SUBCIRCUIT IS FOR THE END PINS OF **
** THE CLP Series 5.13mm MATED CONNECTOR **
** **
********************************************
********************* END ******************
********************************************
T4 1 0 2 0 Z0=66 TD=25PS
.ENDS FTSHDVCLPEL
** END OF END PIN T-LINE SUBCIRCUIT **
********************************************
")
(PinConnections
("1" "2")
("2" "1"))
(XNetConnections
("1" "2")
("2" "1")))))
;******Modified by Cadence Design Systems*****
;[dmlcheck v16-3-85D]
; EXECUTED_AT= Mon March 18 10:51:48 2013
; FILE_MOD_TIME= Mon May 22 09:14:48 2006
; RESULT= 0 errors, 0 warnings
; OPTIONS= -ab
;***End Cadence Design Systems Modification***
To adapt the model for all pin of the connector, I have changed the previous model with this model:
("FPS5220.dml"
(PackagedDevice
("FPS5220"
(ESpice ".subckt FPS5220 1 n1 2 n2 3 n3 4 n4 5 n5 6 n6 7 n7 8 n8 9 n9 10 n10 11 n11 12 n12 13 n13 14 n14 15 n15 16 n16 17 n17 18 n18 19 n19 20 n20 21 n21 22 n22 23 n23 24 n24 25 n25 26 n26 27 n27 28 n28 29 n29 30 n30 31 n31 32 n32 33 n33 34 n34 35 n35 36 n36 37 n37 38 n38 39 n39 40 n40
.param Rc=0.025
R1 1 n1 'Rc'
R2 2 n2 'Rc'
R3 3 n3 'Rc'
R4 4 n4 'Rc'
R5 5 n5 'Rc'
R6 6 n6 'Rc'
R7 7 n7 'Rc'
R8 8 n8 'Rc'
R9 9 n9 'Rc'
R10 10 n10 'Rc'
R11 11 n11 'Rc'
R12 12 n12 'Rc'
R13 13 n13 'Rc'
R14 14 n14 'Rc'
R15 15 n15 'Rc'
R16 16 n16 'Rc'
R17 17 n17 'Rc'
R18 18 n18 'Rc'
R19 19 n19 'Rc'
R20 20 n20 'Rc'
R21 21 n21 'Rc'
R22 22 n22 'Rc'
R23 23 n23 'Rc'
R24 24 n24 'Rc'
R25 25 n25 'Rc'
R26 26 n26 'Rc'
R27 27 n27 'Rc'
R28 28 n28 'Rc'
R29 29 n29 'Rc'
R30 30 n30 'Rc'
R31 31 n31 'Rc'
R32 32 n32 'Rc'
R33 33 n33 'Rc'
R34 34 n34 'Rc'
R35 35 n35 'Rc'
R36 36 n36 'Rc'
R37 37 n37 'Rc'
R38 38 n38 'Rc'
R39 39 n39 'Rc'
R40 40 n40 'Rc'
.ends FPS5220 ")
(PinConnections
(1 n1) (n1 1)
(2 n2) (n2 3)
(4 n4) (n4 4)
(5 n5) (n5 5)
(6 n6) (n6 6)
(7 n7) (n7 7)
(8 n8) (n8 8)
(9 n9) (n9 9)
(10 n10) (n10 10)
(11 n11) (n11 11)
(12 n12) (n12 12)
(13 n13) (n13 13)
(14 n14) (n14 14)
(15 n15) (n15 15)
(16 n16) (n16 16)
(17 n17) (n17 17)
(18 n18) (n18 18)
(19 n19) (n19 19)
(20 n20) (n20 20)
(21 n21) (n21 21)
(22 n22) (n22 22)
(23 n23) (n23 23)
(24 n24) (n24 24)
(25 n25) (n25 25)
(26 n26) (n26 26)
(27 n27) (n27 27)
(28 n28) (n28 28)
(29 n29) (n29 29)
(30 n30) (n30 30)
(31 n31) (n31 31)
(32 n32) (n32 32)
(33 n33) (n33 33)
(34 n34) (n34 34)
(35 n35) (n35 35)
(36 n36) (n36 36)
(37 n37) (n37 37)
(38 n38) (n38 38)
(39 n39) (n39 39)
(40 n40) (n40 40))
(XNetConnections
(1 n1) (n1 1)
(2 n2) (n2 3)
(4 n4) (n4 4)
(5 n5) (n5 5)
(6 n6) (n6 6)
(7 n7) (n7 7)
(8 n8) (n8 8)
(9 n9) (n9 9)
(10 n10) (n10 10)
(11 n11) (n11 11)
(12 n12) (n12 12)
(13 n13) (n13 13)
(14 n14) (n14 14)
(15 n15) (n15 15)
(16 n16) (n16 16)
(17 n17) (n17 17)
(18 n18) (n18 18)
(19 n19) (n19 19)
(20 n20) (n20 20)
(21 n21) (n21 21)
(22 n22) (n22 22)
(23 n23) (n23 23)
(24 n24) (n24 24)
(25 n25) (n25 25)
(26 n26) (n26 26)
(27 n27) (n27 27)
(28 n28) (n28 28)
(29 n29) (n29 29)
(30 n30) (n30 30)
(31 n31) (n31 31)
(32 n32) (n32 32)
(33 n33) (n33 33)
(34 n34) (n34 34)
(35 n35) (n35 35)
(36 n36) (n36 36)
(37 n37) (n37 37)
(38 n38) (n38 38)
(39 n39) (n39 39)
(40 n40) (n40 40))
)))
;******Modified by Cadence Design Systems*****
;[dmlcheck v16-3-85D]
; EXECUTED_AT= Mon March 18 13:54:28 2013
; FILE_MOD_TIME= Mon Mar 18 13:54:25 2013
; RESULT= 0 errors, 0 warnings
; OPTIONS= -ab
;***End Cadence Design Systems Modification***
The element used for all pin in this case is a resistor RC but I have used also the Transmission line. The pins 1...40 are the internal pin of the connector, while the pins n1..n40 are the external pins of the connector.
The log file of the simulator point this message:
**** Tlsim Version 16.2 ****
**** Tlsim command line ****
tlsim -r 1.250000 -o waveforms.sim -dl delay.dl -dst distortion.dst -log tlsim.log -ocycle cycle.msm main.spc
*********************************************************
ABORT: Check your reference to Sckt FPS5220
*********************************************************
*********************************************************
ABORT: Unable to Compile SubCircuit 'FPS5220'
*********************************************************
**** Tlsim Run Times ****
Start time = Thu Mar 21 09:15:18 2013
Finish time = Thu Mar 21 09:15:19 2013
Elapsed time = 0 hours, 0 minutes, and 1 seconds
Can anyone suggest me a solution?