adeel abid
Junior Member level 3
- Joined
- Sep 4, 2012
- Messages
- 26
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,467
i am having problem in design reuse with allegro. i am using hierarchical design in which two external designs are instantiated twice.(total modules = 4(M1,M2,M3,M4)) but after all steps given in capture tutorial and final netlist generation when allegro window opens, it has all the four modules but in M1 half of the some nets(after via) has the net_name of M2 and same is the case with M1. the same is repeated with M3 and M4. please advise what is going wrong? i am using ver 16.0