Allegro Design Entry CIS 15.2 (Netlisting)

[newey]

alg0016

Hello All Expert,

Thanks for reading this post.

I am a beginner at PCB layout. When I tried to create the netlist I get this error below. I really don't know where to begin to solve this problem. Please, help. I'm sorry for the long list below. Just want to give you all the info I can.

Spawning... "C:\Cadence\SPB_15.2\tools\capture\pstswp.exe" -pst -d "c:\cadence\spb_15.2\project2\3740 updated schematic\irf3740-eval-sch.dsn" -n "C:\CADENCE\SPB_15.2\PROJECT2\TEST LAYOUT" -c "C:\Cadence\SPB_15.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Warning [ALG0016] Part Name "CONN PWR 1-P_BINDING_POST_CONN PWR 1-P" is renamed to "CONN PWR 1-P_BINDING_POST_CONN".
#2 Warning [ALG0016] Part Name "HEADER 15X2_0_LABVIEW_CONN_HEADER 15X2" is renamed to "HEADER 15X2_0_LABVIEW_CONN_HEAD".
#3 Warning [ALG0016] Part Name "CONN PWR 1-P_KPA25TP_CONN PWR 1-P" is renamed to "CONN PWR 1-P_KPA25TP_CONN PWR 1".
#4 Warning [ALG0016] Part Name "INDUCTOR_L_FDU1250_0.5UH_0.82MOHM" is renamed to "INDUCTOR_L_FDU1250_0.5UH_0.82MO".
#5 Warning [ALG0016] Part Name "SW DIP-8/SM_SW_8POS_GULL_SW DIP-8/SM" is renamed to "SW DIP-8/SM_SW_8POS_GULL_SW DIP".
#6 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_CLK_EN#" is renamed to "TEST POINT_0_TESTPOINT_47_CLK_E".
#7 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_VR_TT#" is renamed to "TEST POINT_0_TESTPOINT_47_VR_TT".
#8 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_DPRSLPVR" is renamed to "TEST POINT_0_TESTPOINT_47_DPRSL".
#9 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_IR3740-EN" is rena
med to "TEST POINT_0_TESTPOINT_47_IR374".
#10 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_VACOUT" is renamed to "TEST POINT_0_TESTPOINT_47_VACOU".
#11 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_DUAL-PSI#2" is renamed to "TEST POINT_0_TESTPOINT_47_DUAL-".
#12 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_FCCM-DPRSTP#" is renamed to "TEST POINT_0_TESTPOINT_47_FCCM-".
#13 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_C4-FAST-SLOW" is renamed to "TEST POINT_0_TESTPOINT_47_C4-FA".
#14 Warning [ALG0016] Part Name "TEST POINT_0_TESTPOINT_47_DPRSTP#" is renamed to "TEST POINT_0_TESTPOINT_47_DPRST".
#15 Warning [ALG0016] Part Name "IRU1117-33Y_0_SOT223_IRU1117-33Y" is renamed to "IRU1117-33Y_0_SOT223_IRU1117-33".
Scanning netlist files ...
Loading... C:\CADENCE\SPB_15.2\PROJECT2\TEST LAYOUT/pstchip.dat
Loading... C:\CADENCE\SPB_15.2\PROJECT2\TEST LAYOUT/pstchip.dat
Loading... C:\CADENCE\SPB_15.2\PROJECT2\TEST LAYOUT/pstxprt.dat
Loading... C:\CADENCE\SPB_15.2\PROJECT2
\TEST LAYOUT/pstxnet.dat
Error: Line 28 in file C:\CADENCE\SPB_15.2\PROJECT2\TEST LAYOUT/pstxnet.dat:
Reference designators inconsistent in xprt and xnet files
Detected in function: pstFindInstByOldPathName
Error: Line 28 in file C:\CADENCE\SPB_15.2\PROJECT2\TEST LAYOUT/pstxnet.dat:
Error loading the net list file
Detected in function: ddbLoadPstXFiles
#16 Error [ALG0036] Unable to read logical netlist data.

 

[House_Cat]

warning [alg0016] part name

Your warnings are a result of the names you gave to your components. Component names have to be less than 32 characters, and although they were counted, I don't believe spaces are legal characters either. If you count the characters, you will see that the warning is telling you that the name was truncated.

The truncated names can't match up with the netnames using the illegal long component names, so your netlist fails.

Shorten all your component names, and follow the instructions in the Allegro manual.

 

[ee_expert2000]

warning [alg0016]

Your problem is with the component names.
Remember not to used spaces while definig project,directories, and components.
You must take care also with the project names you choose.
Refer to project manager help to know about allowed characters that can be used for project names.
By the way, how do you make use of simulation models for SpecctraQuest?
sincerely