Allegro 16.5 - Propigation Delay etch length through a capacitor

[ekiller200]

I am routing a high speed bus that contains some data diff pairs and a clock diff pair. They must be length matched. The each clock net has termination capacitor in series near the receiver.

How do I create the propitiation rule in CM to sum the trace length from IC to Cap and Cap to IC?

Thanks,

 

[LTimko]

The keyword is pin pairs. Here is a tutorial video how to use it: https://www.youtube.com/watch?v=O4h-BVEEjHM
To be able to do this you need to have Allegro license. Unfortunately, lower licenses will not work.

Regards

 

[marce]

Answered own question looked at some PCIe interfaced, had used caps for termination before, but cant remember the reason so any info would be gratefully received... Thanks

 

[ekiller200]

The keyword is pin pairs. Here is a tutorial video how to use it: https://www.youtube.com/watch?v=O4h-BVEEjHM
To be able to do this you need to have Allegro license. Unfortunately, lower licenses will not work.

Regards

I am using pin pars for the other signals, that do not have in series caps. but with the cap, each net would need two pin pairs, one from the driver to the cap, then one from the cap to the receiver. what I need is for those two pin pairs, plus maybe some information about the cap to all be summed to a total trace length.

I think this has to be done with xnets, but it seems like that is way overkill.

I think I have a work around. I will route receiver to cap.. then use that route length and put it in the pin pair column.. As long I I don't change the route length, I think that will work.