Here are a bunch from nVidia ASIC division: If you know the answers, post them.
2- How many bits do you need if you are adding two 8-bit numbers? How many for 3 8-bit numbers or 4 8-bit numbers?
3- When you are verifying a design at what point do you decide that verification is done and the design can be released?
4- What are the different areas of code coverage? list them.
5- Why is it important to fix transition time even if there are no timing issues?
6- What is your reset strategy?
7- what are the disadvantages of Verilog as an HDL language?
8- What are the advantages/dis-advantages of synchronous vs. async resets?
9- If you have two blocks running at 50 Mhz each and one block of the same gate size, as the two 50 mhz ones, running at 100 Mhz, which one uses less power? Assume voltages are identical.
10- What is your power strategy?
11- What are the challenges of porting a design into an FPGA?
12- How do you fix hold time violations in FPGAs?