1. decode address if it matches memory address space then keep going otherwise ignore the bus transaction
2. apply address to memory
3. for a write:
3a. apply data to memory
3b. strobe write to memory
4. for a read:
4a. capture read data from memory
4b. return read data on AHB bus.
AHB is a 2 phase operation. This allows easy pipelining. The first data and the 2nd address can be sent out simultaneously. Similarly the 2nd data and 3rd address can be sent out at the same time.
I don't know of any special lines for memory in AHB as it is a very generic protocol. It can be used for any application.
You can connect a combination of HWRITE and HREADY to the write enable. You can map the write data directly. There is no way to connect the full and the empty. In case of error, either the master can abort or reinitiate the transaction.
AHB is not meant for interfacing to a FIFO. Only 2 parties can talk over AHB. One is an AHB master and the other is an AHB slave. I don't know how is HRESP related to FULL/EMPTY.
The FIFO FULL and READY are OR'ed and gated respectively with HWRITE in such way so a Write Access to the FULL FIFO will rise HRESP indicating ERROR (the similar for FIFO EMPTY).