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you need to respin it by doing a timing eco ..it depends on how many viol you need to fix and if you have enough spare gates/gate arrays in the design that you can use ...if yes, then you can do a post-mask eco or metal only eco and respin..
Actually you can fix both timing violations with ECO & a re-spin.
@ yadavvlsi: Remember the spare-cells Kbulusu mentioned?
If you have any spare clock buffers or inverters in your design they might help in fixing your hold problem.
Using normal buffers or inverters spare cells to swap with previously used clock buffers & inverters will mean you need to pay close attention to skew effects.
I'm guessing that the timing violations were at marginal values & only swapping a handful of clock buffers/inverters are needed.
Yes, By doing ECO and re-spin we can fix both setup and hold problems. But I talked about the chip that is already fabricated. It is not possible to fix hold in a fabricated chip.
If u have a small setup violation you can fix this by operating at lower frequency.
Hold violations u can address by reducing the overall operating voltage(not recommended).
Yes, By doing ECO and re-spin we can fix both setup and hold problems. But I talked about the chip that is already fabricated. It is not possible to fix hold in a fabricated chip.
If you have a spare buffer in just the right place, you could potentially fix it with a FIB (Focused ion beam - Wikipedia, the free encyclopedia). You would have to be very, very lucky for this to work though.
How about the decreasing the operating voltage a bit but still keep it above the min operating threshold. Will this help in improving the hold time...?
If the violation is on the first flop being fed from an input pin, can we insert an external delay..?
How about the decreasing the operating voltage a bit but still keep it above the min operating threshold. Will this help in improving the hold time...?
If the violation is on the first flop being fed from an input pin, can we insert an external delay..?
How do you plan to accomplish maintaining the temperature in real life scenario?? We take in temperature and P and V during opto and implementation are purely corners and only for reference.
Hi jeevan.life...
Did not understand your reference to the temperature. I am referring to reducing the operating voltage. Can you please explain the relation...
Yes, adding an external delay will affect the setup, but I am assuming we have enough slack on the setup to absorb this delay....
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