After ATPG, there are too many mismatch occurrences in simulation.

[Collang2]

Hi EDA Board users,

After synthesizing and SCAN insertion, I did STA verification in Function mode and SCAN stuckat mode, and I closed the timing in both modes.
Chip is already fab-out, there is no problem with the function operation, the coverage of the Stuckat fault is 99%, and simulation&chip test has passed.



But when I did Transition ATPG with this design, the target coverage of 80% was reached, but in simulation, there are a lot of mismatch.
In my Function SDC, there are timing exception sdc such as set_false_path, set_multicycle_path

1. synopsys에서 pt2tmax.They offer something called tcl, should I reset_path on all paths in design before using this?

2. pt2tmax.Even if I do tcl, there are cases of mismatch.. If I add_capture_mask all of these mismatch, the Fault coverage is too low....

 

[cczhangpjzj]

Hi Collang2, I check the year. It is like almost 2 years ago. About Q1, I think you might want to stop PT right after all the clocks are created, but not yet with any false_path exceptions. And also you must not put those set_clock_groups yet. Only then you are able to get all those paths exceptions extracted completely.

For Q2, ideally if all those path exceptions are included in Q1, I think you should no longer get more mismatches. I think it is better to study the mismatch to understand the true reason?

 

[dick_freebird]

Sounds to me like the scan insertion ate up some timing margin
that you couldn't (according to the timing models) afford, and
seeing it in the timing analysis / at-speed functional?

Maybe you get lucky and it was just a bit of conservative modeling.
Or maybe you find out at high temp low supply tests, nice and
late in the rollout.

Sometimes there are better (less timing-bound) places to put a
scan tap than might be auto-picked, but then you would have
to involve yourself personally in such details. Or maybe it's just
some clock down in the guts that now wants lagged by the same
as the scan mux on some data path. Does synthesis do that kind
of thing? I call it "ballistic timing", use a late clock locally to catch
slow data right, and make it up down the line. All pretty naughty,
I've been told. But tools evolve even if we don't.

 

[maulin sheth]

Tetramax should have a way to read the SDC which consists of FP and MCP. Please check the tetramax Userguide to read the exceptions.
Like for mentor, it has read_sdc command to read the exceptions in ATPG.