[SOLVED] Affect of transient simulation step size on OP-amp stability

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engrMunna

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Hi,
I have an op amp which is basically a folded cascode followed by a common source and then an inverter. I put this in a unity feedback configuration and in transient simulation it works fine. But when I decrease the maximum step size to a small value, the circuit starts oscillating. Why is that changing the step size causes this circuit to become unstable. One more thing that the last stage inverter is biased at the very high gain point, as shown in the DC sweep. Now when I bias this inverter at a lower gain point where the slope of the graph is not that high...then the circuit works even with small step size....but ofcourse since the gain has now reduced..the voltage following also deterioates. ...So baiscally i am having trouble with the step size...and i have to simulate this at a small step size. Please Help
 

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Well, chances are that your opamp is unstable at the high-gain operating point, which should be the typical operating conditions for your opamp.
You are attempting a 3-stage amplifier without any compensation, whereas a 2-stage most often requires some form of compensation.
Do an open loop ac analysis and check for phase margin.
 

Have you done an AC analysis to check for stability? It's quite likely the circuit does oscillate, but the simulator doesn't pick that up with the large step size. I see a lot of gain stages but I don't see any compensation. That's not good for stability.
 

Thanks for your replies...The open loop was in fact unstable...so after compensation the open loop is now stable....the close is giving a wierd phase response. I am attaching the close and open loop response after compensation. And the problem of oscilllation is still there
 

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Dump the inverter, as it's operating point will probably flunctuate greatly as your output passes through its tripping point, and hence changing the ac open loop characteristics as well. To convince yourself, you need to choose an input in which both the inverter MOS are operating in saturation, then do open loop analysis to see whether you are still stable.
 

How come you're only getting 80dB open loop gain at DC? I'd expect better than that with half the complexity.

The part of the circuit shown below looks wrong. If it's supposed to work as a folded cascode, then the top two MOSFETs should be configured as current sources, not a mirror.

 


Yes you are right i changed the circuit now..well i guess the low gain is because my baising current is around 45nA. I have changed the circuit...and now my AC response is stable even without compensation...and if you see the close loop response for unity gain follower its ok too.....but in transient analysis the output sticks to one rail? although close loop and open loop are both stable
 

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Well the problem is the same......my opamp acts as a voltage buffer with unity gain feedback if I reduce the time step....but if i increase the time step it sticks to one rail voltage.....the pictures i attached in the previous post are workig fine with reduced time step but not with increased time step... I am confused
 

This part of the circuit still looks wrong. (This is below the previous part). The bottom two MOSFETs are correctly arranged as a mirror, but what is going on with the one on the top left?

It is supposed to pass signal current from the top to the bottom, so it should either be replaced with a P channel device with the source at the top and the drain at the bottom (i.e. a cascode), or left out altogether.

At this stage I don't care about stability, just trying to get a workable circuit.

 

Hmm I think I get your point you mean to say that the signal current going down into the mirror faces a large resistance due to the nmos that you pointed out....Ok i will try as you suggested and share my results. Thanks
 

engrMunna said:
.....but in transient analysis the output sticks to one rail?
Click to expand...
It looks like you are applying positive feedback instead of negative feedback. Remember, the non-inverting input and inverting input are swapped around because of the inverting output stage.

engrMunna said:
Hmm I think I get your point you mean to say that the signal current going down into the mirror faces a large resistance due to the nmos that you pointed out....
Click to expand...
I thought about that some more. The circuit will work the way you had it.

The source of M20 is connected to the drain of M27, so Vgs of M20 will be quite high. I expect this means it is switched on hard and will have low Rds. So it's effect will be very small, just it's Rds(on) in series with the input to the mirror.

[ot]
Is this an integrated circuit design? To get this to work with discrete components would be difficult and require very careful matching of components.

If so, I'm fascinated. Where it says e.g. "l=400n w:240.0n" next to a MOSFET, is that the length and width of the channel or something? Alternatively, what software are you using? If I know that,I can Google all my stoopid noob questions myself. ;-)
[/ot]
 

I have figured out the problem, the circuit was in fact unstable....but there was a conceptual mistake on my part...thats why I wasnt able to see the reason behind this unstability....anyways I gain-compensated the opanp. and it works now
As for your questions, yes this is an IC design and the W and L are the length and width...I am using Cadence virtuso for schematic design and Spectre for simulation
Thanks for your help !
 

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