AES encryption in vhdl

[anaelgamed]

i downloaded the code of aes in vhdl from OpenCores

but there is some code i don't understand
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x"08" x"09" ..... what is this in the next code and where i can found them
i search about them and not found them in code ???? i can't understand this
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if VALID_KEY_I = '1' and i_BYTE_CNTR4 = 3 then
SRAM_WREN0 <= '1';
elsif v_CALCULATION_CNTR = x"08" then
SRAM_WREN0 <= '1';
elsif v_CALCULATION_CNTR = x"09" then
SRAM_WREN0 <= '1';
elsif v_CALCULATION_CNTR = x"0A" then
SRAM_WREN0 <= '1';
elsif v_CALCULATION_CNTR = x"0B" then
SRAM_WREN0 <= '1';
elsif KEY_SIZE = 1 then
if v_CALCULATION_CNTR = x"0C" then
SRAM_WREN0 <= '1';
elsif v_CALCULATION_CNTR = x"0D" then
SRAM_WREN0 <= '1';
else
SRAM_WREN0 <= '0';
end if;
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SRAM_WREN0 what's the mean of this?

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[TrickyDicky]

x"08" is hexadecimal form of the binary 00001000 for an array of std_logic or bit types.

SRAM_WREN0 sounds like the write enable for SRAM 0.

 

[Suudy]

You didn't post the full code, but from what you did post, I can glean some information.

The x"08", x"09", etc are hexadecimal values. I don't know the type for v_CALCULATION_CNTR, but I suspect it is a std_logic_vector. VHDL '93 allows implicit conversion from a hexadecimal value to a vector. So think of these something like 0x08, 0x09, etc. Or as vectors as "1000", "1001", etc (of course of the appropriate width). Another way to do this is with this (that I think is much clearer) is for v_CALCULATION_CNTR to be unsigned. For example:

signal v_CALCULATION_CNTR : unsigned(7 downto 0);
begin

  process(...)
  begin
   if VALID_KEY_I = '1' and i_BYTE_CNTR4 = 3 then
     SRAM_WREN0 <= '1';
   elsif v_CALCULATION_CNTR = 16#08# then
     SRAM_WREN0 <= '1';
   elsif v_CALCULATION_CNTR = 16#09# then
     ...
  end process;

Where '16#08#' is a hexadecimal number. Note that x"08" works as well since it is a bit vector.

As for SRAM_WREN0, I suspect the core is using a RAM to hold some intermediate, and this chunk of code is driving the write enable on the RAM. You know that SRAM_WREN0 is a signal based upon the type of assignment ('<=' rather than ':=').

 

[anaelgamed]

thanks alot TrickyDicky
do you know ((v_CALCULATION_CNTR )) abbreviation for what?? and also ((v_TEMP_VECTOR)) and((i_FRW_ADD_RD0))

and also ((FF_VALID_KEY ))
and also ((v_KEY_COL_IN0 )) and (( i_INTERN_ADDR_RD0 ))

if you know plz tell me as they are all signals and i need to understand code very well for my graduation project

---------- Post added at 23:00 ---------- Previous post was at 22:56 ----------

thanks alot Suudy
the all codes here
**broken link removed**
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[Suudy]

if you know plz tell me as they are all signals and i need to understand code very well for my graduation project

If this is for a school project, I don't think we should be explaining it to you. Do you need to understand _this_ code? Or just an implementation of AES in general?

thanks alot Suudy
the all codes here
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**

To be honest, I don't think this code is of good quality. It looks to me more like someone versed in general programming, than in hardware design. I know the tools are getting better, but this code would not synthesize to anything respectable.

Better versions to look at are:

AES128 :: Overview :: OpenCores
Avalon AES ECB-Core (128, 192, 256 Bit) :: Overview :: OpenCores

The first one mirrors the AES spec the closes, and it well written. I don't think its architecture is optimized for speed, but it certainly is clear. The second is more structural, but is also well written. If you are just trying to understand an AES implementation in VHDL, these are far better.

If you can do Verilog, there are excellent versions in Verilog as well.

 

[anaelgamed]

and i don't understand this code

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-- RAM
if CE_I = '1' then
if SRAM_WREN0 = '1' then
KEY_EXPAN0(i_SRAM_ADDR_WR0) <= v_KEY_COL_IN0;
end if;
v_KEY_COL_OUT0 <= KEY_EXPAN0(i_SRAM_ADDR_RD0);
end if;

-- Write address
if RESET_I = '1' then
i_SRAM_ADDR_WR0 <= 0;
elsif CE_I = '1' then
if FF_VALID_KEY = '0' and VALID_KEY_I = '1' then
i_SRAM_ADDR_WR0 <= 0;
elsif SRAM_WREN0 = '1' then
i_SRAM_ADDR_WR0 <= i_SRAM_ADDR_WR0 + 1;
end if;
end if;

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---------- Post added at 00:50 ---------- Previous post was at 00:36 ----------

Suudy
really thanks thanks thanks
for your links

they will be better ofcourse

---------- Post added at 01:05 ---------- Previous post was at 00:50 ----------

i need to make this project on fpga and make encryption and decryption on it
is ur link Avalon ((AES ECB-Core (128, 192, 256 Bit) :: Overview :: OpenCores)) and this project can do this ?
and thanks alot for ur help

 

[HRUSHIKESH102]

RESPECTED SIR I ALSO WANTS TO BE AES IN VHDL CODE FOR MY PROJECT PURPOSE CAN U PLZ SEND ME CODE ON hrushikesh102@gmail.com

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can u plz send me guidelines for this project