AES algo key generation process in VHDL

I am currently now working on a project which is exactly not in accordiance with AES algorithm bcoz in AES plaintext and key input is given and corresponding ciphertext has been generated......but in this case cipher and plaintext is provided corresponding key has to be generated.In this part a comparator has been used for comparing the plain and the cipher and a key counter provided for the 10 rounds of key according to key scheduling process.

I have written the code its running fine...o/p is also coming..ok...but the main problem is that i have to minimize the slice registers.till now it is in report 54%.I have done almost everything like some modification in code,through synthesis properties,block ram instantion but still it is not reducing for a single percentage....what should i do now...please anybody help me

well, the only way to reduce register count is to modify the code.
Have you actually instantiated block rams?

I have tried with block ram including with that init file also previously but then some error is coming

why not post the code and errors?

but that will be near about 1800 line code.....

well post the code where you're having problems with a ram block - and the errors...

TrickyDicky said:

well post the code where you're having problems with a ram block - and the errors...

Click to expand...

you need to check your code and remove Register Duplication.
complete all the loops properly, otherwise it will generate extra component.