Advice for System Verilog

[koolnerd]

I have been working on a project using System Verilog where one of the goals is to make the code more efficient. I have been using spare time to read different papers and books on how to program in System Verilog, but given people's experience using System Verilog, if there would be any advice on what to do, what to not do, what leads to a more efficient synthesized circuit etc. It would be nice to have more advice in a single place. Otherwise if there are any resources on writing efficient System Verilog code that would also be incredibly helpful. Thank you in advance

 

[ThisIsNotSam]

you have to be careful with what you mean by efficient, this has a very different meaning in SW than in HW.

when describing digital logic, it is important that you follow some templates for the style of logic that you trying to describe. other than that, assuming you are generally following the templates, you can write a really "dumb" code and a really "smart" code and the synthesis tools will crunch both in the same way. in a way, the synthesis process is really good these days that it is hard to outsmart the tools and get better performance from coding alone. most of the "performance" improvement that you can get come from architectural decisions, not low-level code tweaks.