gaom9
Full Member level 4
Hi,
I am working in a Δ-Σ Fractional-N Frequency Synthesizers, and it cover from 2.3G to 2.7G. I need some advice about the output buffer of it, and this buffer should has 50Ω output matching. The signal to the output buffer is a CML voltage level signal which is from 1.1 to 1.7V with a center frequency of 1.4V. And I want to get a output signal amplitude of Vpp=400mV (sine signal).
And should this buffer be AC couple to the PLL or can be connected directly. and the output bufer can with some off-chip inductor or capacitor.
I have tried a NMOS follower with a Bias-T matching network, but I found the output sine signal of it is not absolutely symmetrical. The upper is 3mV larger than the underside and the signal is with a 412mV Vpp. I want to get a absolutely sine signal output, so is there any other type of output stage can I choose?
Is there any paper about it, please?
Thank you.
Best regards!
I am working in a Δ-Σ Fractional-N Frequency Synthesizers, and it cover from 2.3G to 2.7G. I need some advice about the output buffer of it, and this buffer should has 50Ω output matching. The signal to the output buffer is a CML voltage level signal which is from 1.1 to 1.7V with a center frequency of 1.4V. And I want to get a output signal amplitude of Vpp=400mV (sine signal).
And should this buffer be AC couple to the PLL or can be connected directly. and the output bufer can with some off-chip inductor or capacitor.
I have tried a NMOS follower with a Bias-T matching network, but I found the output sine signal of it is not absolutely symmetrical. The upper is 3mV larger than the underside and the signal is with a 412mV Vpp. I want to get a absolutely sine signal output, so is there any other type of output stage can I choose?
Is there any paper about it, please?
Thank you.
Best regards!