[SOLVED] Advantages of using clock inverters in CTS

[anas66]

Hi,

Does anybody have materials explaining the effect on duty cycle of clock when using clock inverters instead of clock buffers. ??

Thanks in advance ..

Anas

 

[yx.yang]

Hi,

Does anybody have materials explaining the effect on duty cycle of clock when using clock inverters instead of clock buffers. ??

Thanks in advance ..

Anas

Hi, I think there is nothing to do with "INV" or "BUF". The factors that will influence this is:
1): The difference of "INV" or "BUF" cell's rising transition and falling transition.
2): The difference of "INV" or "BUF" cell's rising delay and falling delay.

So you can see the library, the cell named CLKBUF will be better balanced on falling/rising transition/delay than that of cells named BUF/INV.

Thanks.

 

[srihari_adem]

In general we will use inverters in clock tree to balance rise and fall delay mismatches.
Essentially to maintain 50% duty cycle at CK pin of the flops.
Especially when your logic operating on both edges like DDR.

 

[Adam.Yakuvitz]

If you look at the construction of a clock buffer, for most ASIC libraries, its really two inverters optimized back-to-back.
Look at the gate delays of a buffer element and the inverters elements of similar drive strengths and you will see why inverters are used.

-- adam

 

[anas66]

Thanks all ... I got it now ..

Anas