Advantages of implementing the Advanced Encryption Standard in an FPGA

[vackamania]

hi i'm trying to implement the Advanced Encryption Standard in an FPGA...
can anyone tell me the advantage of using an FPGA for this purpose other than the speed of operation...

thanks in advance..

 

[mubeen630]

need help

There are lots of advatage of using FPGA.
1. Ease of progrmming and reprogramming
2. Verification before the silicon is fab
3. Build conceptual HDL designs quickly
4. Build HDL state machines, block diagrams, truth tables, and flow charts
5. Debug and verify your conceptual design
6. Create test bench designs quickly
7. Synthesize your HDL design into a wide range of physical FPGAs
8. Optimize your design for speed and area
Use hierarchical designs effectively
9. Perform static timing analysis
10. Use top-down and bottom-up design techniques
11. Use pre-defined macro functions, IPs and vendor specific macro generators
Reuse design elements
12. Perform gate level verification, compare waveforms against RTL simulation

 

[Iouri]

need help

all math operation will take a lot's fo CPU time and resources. Using FPGA will increase speed and productivity of your sytem. Back fire it is accociate cost with chip on the board, debug/development time, and data on the data bus when you feeding your data, which with some expirience can be captured

 

[vackamania]

Re: need help

There are lots of advatage of using FPGA.
Verification before the silicon is fab

i think the fabrication is not depended on the type of application ..
its universal isn't it ????

 

[Iouri]

need help

I think he mean using FPGA platform towards ASIC development

 

[vackamania]

need help

IMO they are quiet different isn't it..

fpga was developed inorder to caster to the flaws in asic and be more general in applications too isn't it ????

can anyone clariffy on this please.. ???

 

[vackamania]

need help reg. FPGA

please can anyone give some more suggestions please...

 

[vackamania]

need help reg. FPGA

:BOUNCE

 

[staraimm]

Re: need help reg. FPGA

I've implement the AES module in the FPGA under the PCI express bus protocol. The data transfer rate is very fast and the CPU ultimization is very low. Using the openssl , the speed is just 150Mbit/s or so and the CPU ultimization is almost 100%.