Advantage of using Div-2 Frequency Dividers

[ur72]

what is advantage of using div

Hello everybody,

I'm wondering if it is desirable to design a frequency divider for a frequency
synthesizer PLL only with 2^n dividers.

Are there any advantages (speed, power dissipation, easy implementation in CMOS,
noise,...) in avoiding digital counters or other non divide-by-two blocks?

Thanks in advance!
Alex

 

[hmsheng]

Advantages:
High speed: optimize the first divde-by-2, even CML circuit can be used if speed over several GHz;
Low power dissipation: put more current on the first divde-by-2, less on the others; so it's power efficient;
Small size: design the low frequency divide-by-2 with TSPC circuit
Easy implementation: just connect the divide-by-2's

 

[rfsystem]

Disadvantage:

1. Accumulation of jitter noise in the divider chain
2. 2^N does not always match the VCO to reference frequency ratio