ADS931 ADC chip CLK pin connection

[zachs]

Dear all,

I am using a 8 bit 33MHz ADC chip---ADS931 to sample a fast voltage surge signal.

But I have no idea how to connect the CLK pin in order to run the chip at around 30 MHz.
The datasheet just mentions to use high speed or advanced CMOS logic...but I am still not quite sure what I should do for the connection.

So do I need to use any clock generation circuit or clock IC chip???

Thanks.

 

[karesz]

Hi zachs,
don`t worry...
As you can read over ADS clkpin driving, (at fig. Nr.8):
It is not so a big problem, but has some specialities, especially if your Fsignal is up to 10-15MHz. Is it?
If not;
normally you can drive it with an CMOS logic element of the family 74AC, placed not so await from it!
Wher is your clk signal from please?
You must have an CLK-Oscilator or Quartz alone or (my be) synchronized if you have more similar ADCs in your system.
I mean; if its standalone: select an 30 MHz AC-MOS XTAL or clk-oscillator and put it in the neighborhood of your ADC. Than is finished.
Be care with same supply voltages_3V3 or 5V for both/all devices...
I find it as a (possible)good solution:
www.fairchildsemi.com/ds/NC/NC7S14.pdf
Schmitt trigger eliminate some unclear rise/fulltime-situations /noise from your clk-signal if comes from external source.
If your signal has 10-15MHz you must select an exact 50% clk duty cycle source, or you can generate/apply 60 MHz, but must divid it by factor two with an FF, than you hase the needed exact
50% dutyc. as clk. These FF can you route directly to the ADS clk-input, if the distances are not much cm, I say no more as 2-3cm....
Of course in the Clk-region (and analog input too) you need clear gnd/shieldings, good layout overall.
Good luck!
K.

Added after 1 minutes:

Sorry, I wished to write:
As you can read over ADS clkpin driving, (at fig. Nr.8)

Added after 3 minutes:

Also:
As you can read over ADS clkpin driving, (at fig. Nr.8 )

 

[karesz]

Hi zachs,
if you have to measure a peak valu, you will need a peak detector or sample/hold circuit, my be some later...
Your ADC has a full range input bandwith of ca 100MHz, this means: your signal at internal ADC-input is after ca. 3.5sec at the true value.
This means, at thes time will take a sample, but your signal is yet not at the peak!May be you have it only in the 5.th or tenth reading/conversion_I dont know the (time) parameter s of a lighting signal.
Thes is a good job for your PIC.

You have two different frequences to see:
1,
signal repetition rate>> may be mili/pico Hz-or?
2,
needed (3dB!!) system badwith, derived from pulse-edge time, remember-3dB, usually you need more hamonics to process as basic(3dB) frequency, telld as Fouriers "Signal theorem".
3,
I think its better if you plans more phases and build every time more complex your dataaquision system.

To end you need a so called MCA=multi channel analyser to build.
May be you can search for that (& find) on the web.
MCA= you have very speedy conversions and do storage the values from all that, after aquisition is completed or memory is full, you take all the same amplitudes in a group and write a histogramm from their counts...
For exanpl.:
Max. counts are 255(full range): your system aquired 10x 122, 5x 56 &6x 67, with this 3 beams(column) you have have a relative demonstrativ picture of your lightings process...

Please check web & Physics article for that, I must go to make my job!
Good luck!
K.

Added after 2 hours 19 minutes:

I think a Epson SG-310 SCF C 32.0MHz, Farnell 127-8068 is a good compromiss as ACMOS-Clk osci, and relative cheap...
It NEEDS 3V3!
I believe, its is bessser to design on 3V3, then needs less power for same speed.
Other Possibility is to take 32 MHz Quartz to PIC & buffer it, with Tiny ACMOS SOT-5 ICs, to ADS931, but all in small distances please...
K.

 

[zachs]

karesz:

Thanks a lot for your reply, I really appreciate it !!!

Yes, I still have one doubt regarding to the oscillator,(maybe you think it's stupid) I think the crystal oscillator usually generates sine wave at certain frequency, eg: in my case at 32MHz, but how can I make waveshape to square wave in order to connect to CLK pin, in my mind, clock signal is always in square wave form. (Am I right??)

But I also read some notes saying that some ADC application even use sine wave as clock signal as sine wave has less harmonics.

The ADS931 data sheet doesn't mention either sine or square wave should be provided for the CLK pin.

Hope you can enlighten me.

Thanks a lot.

 

[karesz]

Zachs; No problem!
If your signal is sinusoid & you need squares/pulses:
1,
you can apply an amp with possible big amplifying (calculated output amplitde = 100-1000x "over powersupply voltage", also it will be limited): your rise time will be shortened to1/00-1000x_ it is not the best way, but one possible to go on...
2,
you must apply an comparator, what in princip is the same, but practically not the self effect & need no rrecovering time as by "overamplifying"...

In all cases, these (today clks) oscillators has generelly squares as output signal. Sinus qurtz-oscis are normally the "(L-C) tuned stages/ solutions".
Sinus qurtz osillators are this time the spcialised as very stabile time references, some seldome...

Check datasheet please:
www.brookdale.com/saronix/st4100.pdf
You will read:
edge times= at 2nsec>>>=square as waveform...

ADS931`s datasheet tells for you(corner of left top, side 12): it need a clk signal with edges of ca. 2 nsec, also=sqarewaves, we say: pulses (duty cycle at 50%)!

You must datasheets every time very exactly read, some time between sentences to:-(...
K.

 

[karesz]

Hi zachs,
I didnt forget yopur project_will drow some for you...
K.

 

[zachs]

Thanks a lot karesz and Happy new year,

Currently I'm trying to look for the suitable crystal oscillator. But Singapore Farnell doesn't have st4100 which you recommend (with edge time 2ns, just match the optimum requirement set by the data sheet), the fastest oscillator they have edge time is 6ns.

And I am re-designing the whole driving circuit according to the reference application note provided by Texas Instrument's Engineer. The link is https://focus.ti.com/lit/ug/slau007d/slau007d.pdf

 

[karesz]

Don`t worry Zasch!
I think, your Farnell-XTAL osci with 6ns + a ACMOS (Tiny-CMOS) Speedy-driver has your solution too)

Are you from Singapore pls?
K.
I attached yet my circuit-idea for your aquisitionsproblem...

I agree with meanings, that hier is Clk edge-time not so a very big problem, this is the reason why I wrote, that "a" clk-modul of 6ns edges must be OK too.
In all cases I belief, that in neighborhood of ADC is recommendable to apply a Tiny_Schmittrigger_ speedy buffer, as I proposed earlyer: NC7S14.
sincerely!
K.

 

[FvM]

As a small supplement to the verbose suggestion that have been already made: The clock source requirements strongly
depend on your signal processing application. The minimum requirement is a logic level according to data sheet specification.
The duty cycle, rise-time and jitter specification are mainly influencing the ADC's dynamical performance. As your application
is time-domain related data acquisition, besides a small impact on static linearity, the clock parameters can be expected
less critical. This would be different in a frequency domain application, e.g. a digital receiver, where clock uncertainty
is directly converted into phase noise.

The best solution for a clock source also depends on the overall data path design, that hasn't been mentioned yet. In a typical
PLD design, the clock would be most likely sourced from the PLD/FPGA processing the ADC data.

 

[karesz]

Hi zachs,
how is situation with your design!
K.