I'm afraid I caused confusion with my post on grouping pins in the previous thread.
There is a mistake with the diode (P4/P5/P7).
By grouping pins P4 and P5 into one port, you enfore a two terminal device: the only way of P4 current is to leave at P5 then. But your device has three pins, not two, so you need to ungroup the pins at the diode and have three independent ports.
When using EM results in schematic, grouping of pins to ports is not required here. The wiring of EMmodel at schematic level is sufficient, there is no need to group the pins into one port with explicit ground. You can leave all pins with global ground (substrate backside) and make connections at schematic level.
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Calibration: TML is ok for your input port, but only works if both pins are located on the same plane at the polygon boundary. It seems that P12 is located inside the polygon, then TML will not work, and it will switch calibration to "None" behind the scenes.
Using calibration "none" for the other elements is ok here, to keep it simple. The layout looks not finalized (detailed) anyway, and port cal has very little influence at your frequency of interest. Details like proper component size and footprint have much more effect than port cal.
Best regards
Volker (Keysight Certified Expert EDA)
Thank you so much.The example from my website that you linked shows importance of port ground reference. If all your ports share the same global ground you are "safe" to use that in layout look-alike.
Grouping pins to ports has an effect on the "raw" S-parameters from EM simulation. If you do NOT group them, you have maximum degrees of freedom in wiring the EM Model.
Believe me that you should not group pins to ports for the case show above. The required connections are made at schematic level, so don't worry!
Dear volker,Have you changed the EM model back to ports with global ground?
Create a test schematic with the look-alike and two ports (ADS element: Term). One port is conected to P8, the other port is connected to P9. Show the impedance into each of these ports in Smith chart, for wideband sweep from DC to 3 GHz. Both should be close to short circuit.
You should test things step by step. Did you do the tests that I described above?
You need to define EM frequency range starting at DC, did you do that?
You can replace parts of the schematic by EM Model step by step, to see what is critical. Troubleshooting your simulation in a systematic way is part of the engineering job. Test your EM results if they make sense at DC also.
I changed the frequency range from 0 to 4GHz.
That's a surprising result. I just changed the frequency range, but the efficiency went back up to 64 percent!!
I have an additional question, is there any difference between using C_Pad with port and just connecting ports without Pad to the space where capacitors will be used?
Thank you for reply.This is no surprise, because your schematic simulation covers 2.4 GHz and DC. If you EM simulate at 2.4 Ghz only, there is no information on DC behaviour in your EM Model, and ADS will use extrapolation. But extrapolation from 2.4 GHz down to DC is very inaccurate here.
I don't understand your question. Momentum simulates the layout, no more and no less. If you want to include the effect of component pads (more area = more capacitance to ground) the pads must be included in layout. Using C_Pad is one possible way to include them.
It is always a good idea to EM-simulate the layout that you will build in hardware. Your layout has pads, so you better simulate them.
Thanks for your kind reply.Of course, more accurate modelling of the actual layout will improve accuracy. I haven't used C_Pad in my Momentum models, if it doesn't support automatic partitioning you might need to add ports yourself.
But this forum cannot replace Momentum tutorial and training, sorry for that. There are many good youtube tutorials by Anurag: https://www.youtube.com/channel/UCuo4ZHW4J5k0EmuyKG8kYEA
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