ADS error message:The internal timestep is too smaller. Help

[davison7]

ads internal time step error

Hi! everybody,

I simulate a frequency divider with the ADS transient simulator and also do the layout extraction with the momentum. However when I put the extraction data block (layout.sp) into the circuit in order to finish the post-layout simulation, the simulation/synthesis messages appear a error that shows "Error detected by hpeesofsim TRAN analysis 'Tran1'. Internal timestep 6.25e-26 too small at time 4.59168e-10."
* The frequency divider has the input operation frequency of 24 GHz, so I setup the simulated time range of 0 - 20 ns and the Max. time step of 1 ps for the transient simulator.

I try to setup the smaller timestep (about 1 fs) for solving the probelm, but it need to spend a very long time on the simulation. So what reasons cause the above error? May everbody shows the improvement methods or the solutions? Thanks.

 

[Abhishekabs]

internal timestep too small ads

Hi davision7,
At this moment I don't have ADS, but I can suggest you few things.
1) Enable Convolution.
2) Use 0 PS to 1ns. with time step 10 PS.
or 0 fs to 100 PS with time step 10 fs

Please try this & let us know.

 

[kspalla]

error detected by hpeesofsim during sp analysis

Can you share the design with us?
You can send your design to agilent tech support too.

 

[Abhishekabs]

internal time step too samll + ads

see following image.I hope this helps.

BR,
Abhishek

 

[erikl]

timestep error

Mostly for such error messages, there is/are one (or more) node(s), who's voltage changes more than a maximum limit (some simulator parameter) even during such a tiny shown timestep. Further error messages should give you more info about this/these failing node(s). In many cases, this occurs because of a discontinuity in some characteristic.

 

[moghtada]

agilent internal timestep too small at time

you should add few capacitor (about 100M ohm @ 24GHz) at all nodes in your schematic then simulate it.
yours

 

[davison7]

ibis + internal time step is too small + ads

thanks for Abhishekabs' and kspalla's suggestion,

Finally I solve the problem with defining the max frequency about 100E+009 Hz in covolution function of the transient simulator. If the max frequency is default value, the simulator will change the frequency in very hign value for fitting the source bandwidth. A discussion for this situation maybe the layout extraction has some errors(ex,the port setup is incorrect or the layout has wide discontinuous plane)

 

[tdf]

Re: ADS error message:The internal timestep is too smaller.

Hi there,

I got the "time step is too small" problem too, not in transient, but in envelope analysis.

But it seems that in envelope configure doesn't include convolution.

Can any one resolve it?

Thx,

tdf.