davison7
Junior Member level 2
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ads internal time step error
Hi! everybody,
I simulate a frequency divider with the ADS transient simulator and also do the layout extraction with the momentum. However when I put the extraction data block (layout.sp) into the circuit in order to finish the post-layout simulation, the simulation/synthesis messages appear a error that shows "Error detected by hpeesofsim TRAN analysis 'Tran1'. Internal timestep 6.25e-26 too small at time 4.59168e-10."
* The frequency divider has the input operation frequency of 24 GHz, so I setup the simulated time range of 0 - 20 ns and the Max. time step of 1 ps for the transient simulator.
I try to setup the smaller timestep (about 1 fs) for solving the probelm, but it need to spend a very long time on the simulation. So what reasons cause the above error? May everbody shows the improvement methods or the solutions? Thanks.
Hi! everybody,
I simulate a frequency divider with the ADS transient simulator and also do the layout extraction with the momentum. However when I put the extraction data block (layout.sp) into the circuit in order to finish the post-layout simulation, the simulation/synthesis messages appear a error that shows "Error detected by hpeesofsim TRAN analysis 'Tran1'. Internal timestep 6.25e-26 too small at time 4.59168e-10."
* The frequency divider has the input operation frequency of 24 GHz, so I setup the simulated time range of 0 - 20 ns and the Max. time step of 1 ps for the transient simulator.
I try to setup the smaller timestep (about 1 fs) for solving the probelm, but it need to spend a very long time on the simulation. So what reasons cause the above error? May everbody shows the improvement methods or the solutions? Thanks.