Adjustable AC load 100W

I would like to build an adjustable AC load that will work from 10V up to say 250Vac, about 100W

Google search led to this lower power, lower voltage circuit. If I change the FETs to 600V, do you think it will work?

You'll need to change the load resistor, and maybe your scaling resistors. And make sure your FETS can handle the current and power. You may need to dissipate a LOT of power, depending on how you set this up.

Because of the ver large power dissipation Barry mentions, most likely you will have to parallel two, three or more Mosfets.

The Mosfet's gate is highly capacitive, and many opamps may oscillate with large capacitances.

At least for me it is not too clear how much current would be sinked by this circuit along the cycle of the waveform. In having no proportional relation with the current and the input voltage, the circuit would not act as a resistive load. Considering that this topology is like working as a comparator rather like an amplifier, there is expected a kind of unlinearity.

barry said:

You'll need to change the load resistor, and maybe your scaling resistors. And make sure your FETS can handle the current and power. You may need to dissipate a LOT of power, depending on how you set this up.

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I was thinking of making a blow-through design, similar to the HP power supplies, for example: https://i.ytimg.com/vi/quOQ-Wedxjc/maxresdefault.jpg

I cobbled together the circuit on a breadboard and tested it at low current (100-200ma). It works more or less.

I'm somewhat mystified as to why the output current is reasonably close to sinusoidal while the DRV signal output from the opamp is a rounded square wave, I would have expected the opamp to provide a sinusoidal voltage waveform to the gate based on the current feedback signal. Now that I think about it I guess as the FET's start to actually turn on (transition from linear mode closer to "on") very little extra voltage is required to drive significantly more current so the voltage DRV (gate) signal has to be non-linear to give a linear output current. Does that make sense or am I out in left field with my interpretation?

I also see some zero cross distortion (small glitch on positive edge) as the current is increased, it would be nice to get rid of it.

Jester said:

very little extra voltage is required to drive significantly more current so the voltage DRV (gate) signal has to be non-linear to give a linear output current. Does that make sense or am I out in left field with my interpretation?

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When I tested mosfets I've seen (or so it appeared) conductivity go from min to max as I changed bias voltage by just a few volts. The effect may be different with different supply voltages, or different loads, etc.

a simple alternative is to have a resistive and bulb loads.
With all meters (volt/current/power) on the loadside , you can have an adjustable ac load.

Hi,

I'd add an R between R4 and C5. Then lower C5.
This makes it more easy for the Opamp to drive the Output.
More precise because faster regulation, less ringing.

Klaus

I'd add an R between R4 and C5. Then lower C5.
This makes it more easy for the Opamp to drive the Output.
More precise because faster regulation, less ringing.

Click to expand...

In addition possibly a series resistor to C5 to increase the phase margin (turning a pure I controller into PI).

Zero crossing distortions are however unavoidable "by nature" of the simple circuit. The OP output needs to "jump" by a considerable amount to steer both polarities, limited loop gain and OP slew rate as well as MOSFET input capacitance don't allow this to happen in no time.

I guess, the circuit can be an acceptable compromise for low frequency. Otherwise you need separate control loops for both polarities, and a considerably more complex circuit.

Hi,

you could use a bridge rectifier and use one_direction (one quadrant) current control.

Klaus

KlausST said:

Hi,

I'd add an R between R4 and C5. Then lower C5.
This makes it more easy for the Opamp to drive the Output.
More precise because faster regulation, less ringing.


Klaus

Click to expand...

Klaus, I will give your suggestion a try, thoughts on the resistor value?

Hi,

1k, 15nF (gives an fc of about 10kHz. Modify according your taste)

Klaus

Next step is to see if I can get this to work at significantly higher voltage and current.

If I'm interpreting the SOA curve correctly it looks like I might squeeze about 20A@24Vac, 1.75A@120Vac, 240vac looks marginal even at 100mA, does that look correct?
https://ixapps.ixys.com/DataSheet/DS99990(IXTK-TX32P60P).pdf

IF I place a diode is parallel with the body diode so that each FET is only conducting current 1/2 the time (assuming the external diode has a lower Vf) could I perhaps squeeze a bit more current from these FET's?

KlausST said:

Hi,

1k, 15nF (gives an fc of about 10kHz. Modify according your taste)

Klaus

Click to expand...

Klaus,

With 1k, 15nF the system is stable, however the zero-cross drop out is quite significant, however with a 30nF and lower R, I tried 470r, and 220r the ZC glitches are almost acceptable. I was able to drive the current up to > 1Arms even with the small FET's. I have some larger FET's on order. So I'm moving in the right direction.

If I add parallel FET's for increased current capability, can I simply parallel them or should I use individual gate resistors and or gate resistors and an additional opamp?

It seems problematic to parallel at all in a linear application since small variations in threshold will make a large difference in resulting current. In other words current/wattage sharing may be very poor.

The control circuitry is cheap and small compared to the cost/size of the fets and heat sinking so I'd duplicate the entire circuit and have two complete circuits running in parallel. That guarantees 50/50 load sharing.


It seems there might be some value in trying to bias the gates of the two fets such that when the opamp is outputting zero both gates are biased towards their on threshold (just below it). I.E. pull the gate of the N up and the gate of the P down. The goal is to minimize the op-amp's jump at crossover. Though adding R to create this network would compromise bandwidth. Zeners would work for this too. Though it will never be perfect because the thresholds vary too much (between devices and over temperature).

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Jester said:

Next step is to see if I can get this to work at significantly higher voltage and current.

If I'm interpreting the SOA curve correctly it looks like I might squeeze about 20A@24Vac, 1.75A@120Vac, 240vac looks marginal even at 100mA, does that look correct?
https://ixapps.ixys.com/DataSheet/DS99990(IXTK-TX32P60P).pdf

IF I place a diode is parallel with the body diode so that each FET is only conducting current 1/2 the time (assuming the external diode has a lower Vf) could I perhaps squeeze a bit more current from these FET's?

Click to expand...

The diode is quite a small percentage of the losses in this linear application so another diode won't help unless you try to push much lower than the 24VAC you've suggested.

And keep in mind the big picture, your main fets are burning a lot of watts. Anything that takes significant watts from them will have thermal problems of its own. It's probably best to keep all the watts in your two main fets and focus on how to heatsink them.

Hi,

With 1k, 15nF the system is stable, however the zero-cross drop out is quite significant, however with a 30nF and lower R, I tried 470r, and 220r the ZC glitches are almost acceptable

Click to expand...

If you want the zero cross to improve, you should consider lower value capacitors instead of higher value capacitors.

Klaus

It seems there might be some value in trying to bias the gates of the two fets such that when the opamp is outputting zero both gates are biased towards their on threshold (just below it). I.E. pull the gate of the N up and the gate of the P down. The goal is to minimize the op-amp's jump at crossover. Though adding R to create this network would compromise bandwidth. Zeners would work for this too. Though it will never be perfect because the thresholds vary too much (between devices and over temperature).

Click to expand...

Everything depends on the distortion specification of the load.

Presently, the circuit has two disadvantages:
- zero crossing distortion by polarity changeover
- zero crossing distortion by substrate diode voltage drop

To tackle both, you would need a circuit (most likely with two control OPs) that turns the other FET on in reversed operation and starts current regulation from on-state rather than off-state after each zero crossing.

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Or the other way around, if the diode voltage drop is well acceptable, a speeded-up version of the present circuit should do.

More progress, we're getting closer

With 30nF and 220r, the ZC dropout was 32 degrees, I tried successively smaller capacitors until I reached 1000pF, at this point the ZC distortion is acceptable from my perspective < 5 deg dropout (see below). Hopefully the system will remain stable with this filter so high (700kHz)?

The DRV signal now has a much more noticeable spike at each zero cross, however it appears to be well within the +/-20V max Vgss limit, so I think it should be okay?




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Thinking ahead to a higher voltage version, I expect there be a problem with Vgs on the upper FET.

If we assume 100Vrms, the peak voltage at the source of the upper FET would be 140V during the positive peak of the cycle, meanwhile the opamp would be + 10V max, so Vgs would be 130V, does this sound correct?

Comments welcome