Additional spectrum frequency in the measurements of amplifier performance

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Alipoursaadaty

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Hello,

I have designed a wideband ultra-low noise high gain amplifier with a voltage gain higher than 80 dB, input referred noise less than 1 (nV/sqrtHz), and a BW higher than 250 MHz. However, it is oscillating in higher gain, and I have to reduce the gain to achieve some measurement results.

In 60 and 70 dB voltage gain, it is near to oscillation, and when I want to apply a sine wave with 0 dBm and 10 MHz specifications, I can see the amplified output signal. However, other spectrum frequencies are appearing. The range of these frequencies starts from the 3-dB BW of the amplifier like 400 MHz and this frequency interval is higher than 100 MHz. Also, some other frequencies like 1 GHz can be seen in the spectrum analyzer. I tried to change the sine wave generator and used another one to make sure if these frequencies were produced by the generator or not. However, the problem was not solved.

Does anyone know how I can solve this problem?

I must mention that when I turn the signal generator off (no input signal), these frequencies disappear.

Regards,
 

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Is this an integrated design, chip, or discrete design ?

If later post schematic, proto PCB board layout image(s).


Regards, Dana.
 

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danadakk said:
Is this an integrated design, chip, or discrete design ?

If later post schematic, proto PCB board layout image(s).


Regards, Dana.
Click to expand...
This is an integrated circuit design.

The structure is so simple. 4-stage amplifier. Every stage is a simple fully differential amplifier using an inverter-based structure.
 

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If you cannot eliminate parasitic oscillations on board then you must isolate the stages that couple to non-inverting inputs. (+ve FB) This includes conductive decoupling by filter Vdd to each stage that has poor PSRR. Modifying the board with ferrite and dielectric in appropriate amounts and places, you can observe changes in spurious spectrum to isolate the root cause. (e.g. lossy ferrite and 1~100 pF C0G caps.

What output do you get with input shorted? Output terminated?
Are you using Non-Inverting input if differential?
Are outputs differential?
Any voltage or current feedback?

Here are common layout suggestions for 1GHz type linear buffers.


 
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Thank you for your response. At this time the problem is not parasitic oscillations, the problem is that when I apply any input signal to the differential input nodes, I see some parasitic signals in the spectrum around the high frequencies. However, when I turn the input signal off, these frequencies are removed although the amplifier works without any input signal and is in the turn-on mode.

Why does it have poor PSRR when the power supply of each stage is separated from the others?

Is it good for connecting all VDD and GND nodes using ferrite beads? For the next fabrication, I decided to put separate VDD and GND nodes for each stage to prevent any loop between input and output nodes and connect them using inductors or ferrite beads. However, they have oscillation frequencies, and for the common mode signals, the common mode amplification is raised in the simulation which will cause a degradation in CMRR. I am just concerned about this problem.

What output do you get with input shorted? Output terminated? Ans: Noise at the output reduced.
Are you using Non-Inverting input if differential? Ans: It is a fully differential amplifier
Are outputs differential? Ans: Yes
Any voltage or current feedback? Ans: No feedback between the input and output nodes. Only between each stage for fixing the DC bias point. Amplifier is a 5-stage architecture. The possible feedback is only with VDD of stages 2, 3, and 4. Also, The GND node of them has been connected inside the chip (in layout).
 

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Try testing with single ended inputs then common mode inputs to check for patterns in spurious modes with various amplitudes.
Can you shift the spurious frequency with your grounded finger easily?
Would a grounded lid improve it?
Perhaps the common DC bias affects gm too fast and need damping. .i.e. Is there an error amplifier for Vcm-out to Vcm-in?
Do you have on chip damping resistors on each output like 10 ohms?

We can only guess what your layout looks like for your test jig.
Here is the LMH5401RMST 8-GHz layout.

If you need a balun, TI recommends the Marki B0100 or PicoPulse Labs 5310A
 
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Can you shift the spurious frequency with your grounded finger easily? No
Would a grounded lid improve it? No
Perhaps the common DC bias affects gm too fast and needs damping. .i.e. Is there an error amplifier for Vcm-out to Vcm-in? Sorry, I didn't understand it.
Do you have on-chip damping resistors on each output like 10 ohms? If you mean a series resistor with he output node, no
 

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You may have to model the parasitics L, C to match your measurements to understand why it is unstable. I use 0.5 nH/mm +/-50% depending on l/w ratio and 3pf/mm over a ground plane. You can scale this down to 0.5 pH/um and 3fF/um and then figure out out coplanar crosstalk parameters too and see how that works. Your mileage may vary.

If you succeed in making an amplifier with this massive GBW to work in a chip, it will be your personal record.
 
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Thank you for your response.

I must design for the second time. However, the first one has some results with 60 to 70 dB gain, less than 1 nV/sqrt(Hz), and BW higher than 250 MHz.

But the design is for gain higher than 80 dB. Power consumption is the same as the schematic.

However, I am so concerned that I have the same problem with the second design. I cannot model this oscillation using Cadence. In Cadence, I was not able to see self-oscillation. Do you know how can I find out the method to model this oscillation before fabrication? I put the wire-bond effect and modeled it for the first tape-out. But, there was no oscillation in the simulation.

Regards,
 

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D.A.(Tony)Stewart said:
Is each 20 dB stage inverting? What happens with mutual coupling between 2 stages non-inverting, if you model some parasitic crosstalk between non-inverting stages in fF.
Click to expand...
I tried to connect two amplifiers in series together without any oscillation and 40 to 50 dB voltage gain for each one. In the signal analyzer, I could achieve an 84 dB voltage gain. However, the signal at the oscilloscope could not be detectable. Because the internal noise of the amplifier is getting amplified, and input signal cannot be seen on the oscilloscope. Therefore, I found out that as this amplifier has high gain and high bandwidth, it is getting saturated for a higher voltage gain than 65 or 70 dB. My designed amplifier works with a 1-V power supply for amplification stages. Also, the GBW would be 9 GHz. considering half of this bandwidth for the output noise RMS voltage (4.5 GHz), 3160 for voltage gain (70 dB), and considering a 1 nV/sqrt(Hz) as the input-referred noise of the designed amplifier, the output noise RMS voltage would equal with:

No=sqrt((Ni^2)*BW)*Av=sqrt((10^-18)*(4.5*10^9))*3160=0.212 Vrms

The peak-to-peak noise voltage at the output would be 6*No=1.27 Vp-p. Therefore, the amplifier is getting saturated by the internal noise of itself.

Moreover, I could model it in the simulation at Cadence by enabling transient noise at the Tran analysis.

On the other hand, oscillation is modeled in the schematic by using the wire-bond model. Also, the wire bonds are the cause of system oscillation, and I simulated its effect on the Cadence schematic simulation.

Would you please let me know if there is a method to prevent this type of oscillation?

I wanted to share my experience during this time with you and other designers that they may need in the future. Finally, thank you for your guides and other people's help during this measurement process.

Regards,
 

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